Functional Description - 3.5 English

The Zynq™ UltraScale+™ MPSoC Processing System wrapper instantiates the processing system section of the Zynq UltraScale+ MPSoC for the programmable logic and external board logic. The wrapper includes unaltered connectivity and some logic functions for some signals. For a description of the architecture of the processing system, see the Zynq UltraScale All Programmable MPSoC Technical Reference Manual (UG1085) [Ref 1] . This Figure shows the architecture of Processing System (PS) IP wrapper.

Figure 2-1: PS IP Wrapper Architecture

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The core connects the interface signals with the rest of the embedded system in the programmable logic. The interfaces between the processing system and programmable logic mainly consist of three main groups: the extended multiplexed I/O (EMIO), programmable logic I/O, and the AXI I/O groups. The PS Configuration Wizard (PCW) configures the Zynq UltraScale+ MPSoC Processing System Core. Double click PS IP on the AMD Vivado™ IPI (Inter-Process Interrupts) canvas to access the PCW. This Figure shows the PCW configuration on Zynq UltraScale+ MPSoC Processing System. The core performs the functions described in the following subsections.

This Figure shows a top-level block diagram.

Figure 2-2: Zynq UltraScale+ MPSoC Top Level Block Diagram

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