There are three interfaces through which the AMD Zynq™ UltraScale+™ Processing System core can access the PL side peripherals and vice versa. For more details, see the individual sections of AXI_HP and AXI_ACP interfaces in the “Interconnect” chapter of the Zynq UltraScale All Programmable MPSoC Technical Reference Manual (UG1085) [Ref 1] .