Port Descriptions - 3.5 English

The signals for the design are listed in the following tables.

Table B-1: SD/SDIO/eMMC: I/O Configuration
I/O Configuration	Slot Type
Signal Name	SD 2.0	SD 3.0	SD 3.0 AutoDir	eMMC
sdioX_bus_pow	bus_pow	bus_pow	bus_pow	hwreset
sdioX_wp	wp	wp	wp	N.A.
sdioX_cd_n	cd_n	cd_n	cd_n	N.A.
sdioX_cmd_out	cmd_out	cmd_out	cmd_out	cmd_out
sdioX_clk_out	clk_out	clk_out	clk_out	clk_out
sdioX_data_out[3:0]	data_out[3:0]	data_out[3:0]	data_out[3:0]	data_out[3:0]
sdioX_data_out[4]	N.A.	sel	sel	data_out[4]
sdioX_data_out[5]	N.A.	dir_cmd	N.A.	data_out[5]
sdioX_data_out[6]	N.A.	dir_dat0	N.A.	data_out[6]
sdioX_data_out[7]	N.A.	dir_dat1	N.A.	data_out[7]

Table B-2: CAN0
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
can0_phy_tx	O	CAN bus transmit signal to first CAN physical-side interface (PHY)
can0_phy_rx	I	CAN bus receive signal from first CAN PHY

Table B-3: CAN1
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
can1_phy_tx	O	CAN bus transmit signal to second CAN PHY
can1_phy_rx	I	CAN bus receive signal from second CAN PHY

Table B-4: Event IO
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
pl_ps_eventi	I	Causes one or both CPUs to wake up from a wait for event (WFE) state.
ps_pl_evento	O	Asserted when one of the CPUs has executed the Send EVENT (SEV) instruction
ps_pl_standbywfe	O	CPU standby mode: asserted when a CPU is waiting for an event
ps_pl_standbywfi	O	CPU standby mode: asserted when a CPU is waiting for an interrupt.

Table B-5: FIFO_ENET0
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
enet0_tx_r_data_rdy	I	When set to logic 1. Indicates enough data is present in the external FIFO for Ethernet frame transmission to commence on the current packet.
enet0_tx_r_rd	O	Single tx_clk clock cycle wide active-High output requesting a 32-bit word of information from the external FIFO interface. Synchronous to the tx_clk clock domain.
enet0_tx_r_valid	I	Single tx_clk clock cycle wide active-High input indicating requested FIFO data is now valid. Validates the following inputs: tx_r_data[31:0], tx_r_sop, tx_r_eop, tx_r_err and tx_r_mod[1:0]
enet0_tx_r_data	I	FIFO data for transmission; this output is only valid while tx_r_valid is High.
enet0_tx_r_sop	I	Start of packet. Indicates the word received from the external FIFO interface is the first in a packet. This input is only valid while tx_r_valid is High.
enet0_tx_r_eop	I	End of packet. Indicates the word received from the external FIFO interface is the last in a packet. This input is only valid while tx_r_valid is High.
enet0_tx_r_err	I	Error, active-High input indicating the current packet contains an error. This signal is only valid while tx_r_valid is High and can be set at any time during the packet transfer.
enet0_tx_r_underflow	I	FIFO underflow. Indicates the transmit FIFO was empty when a read was attempted. This signal is only valid when a read has been attempted and the tx_r_valid signal has not yet been received.
enet0_tx_r_flushed	I	FIFO flush in progress. Indicates the transmit FIFO is currently removing any residue data content.
enet0_tx_r_control	I	tx_no_crc, set active-High at start of packet (SOP) to indicate the current frame is to be transmitted without crc being appended. This input is only valid while both tx_r_valid and tx_r_sop are High.
enet0_dma_tx_end_tog	O	Toggled to indicate that a frame has been completed and status is now valid on the tx_r_status output. Note that this signal is not activated when a frame is being retired due to a collision.
enet0_dma_tx_status_tog	I	This signal must be toggled each time either tx_end_tog or collision_occured are activated. Indicates that the status has been acknowledged.
enet0_tx_r_status	O	[3]: fifo_underrun—status output indicating that the Ethernet media access control (MAC) transmitter has underrun due to one of the following conditions. Data under run indicated by tx_r_underflow input from the external FIFO interface during the last frame transfer. Reset once efifo_tx_status_tog changes logic state. [2]:collision_occured—status output Indicating that the frame in progress has suffered a collision and that re-transmission of the frame should take place. [1]: late_coll_occured—status output indicating that the frame in progress suffered a late collision and can be optionally retired. [0]:too_many_retires—status output indicating the frame in progress experienced excess collisions and was aborted.
enet0_rx_w_wr	O	Single rx_clk clock cycle wide active-High output indicating a write to the external FIFO interface.
enet0_rx_w_data	O	Received data for output to the external FIFO interface. This output is only when rx_w_wr is High.
enet0_rx_w_sop	O	Start of packet. Indicates the word output to the external FIFO interface is the first in a packet. This output is only valid when rx_w_wr is High.
enet0_rx_w_eop	O	End of packet. Indicates the word output to the external FIFO interface is the last in a packet. This output is only valid when rx_w_wr is High.
enet0_rx_w_status	O	Status signals, valid when rx_w_eop is High and rx_w_err is Low, otherwise driven to zero. [29]:Rx_w_type_match—indicates the received frame was matched on type ID register [28]:rx_w_add_match4—indicates the received frame was matched on specific address register4 [27]:rx_w_add_match3—indicates the received frame was matched on specific address register3. [26]:rx_w_add_match3—indicates the received frame was matched on specific address register2. [25]:rx_w_add_match3—indicates the received frame was matched on specific address register1. [24]:rx_w_ext_match—indicates the received frame was matched externally by the eam input pin. [23]:rx_w_uni_hash_match—indicates the received frame was matched as a unicast hash frame. [22]:rx_w_mult_hash_match—indicates the received frame was matched as a multicast hash frame. [21]:rx_w_broadcast_frame—indicates the received frame is a broadcast frame. [20]:rx_w_prty_tagged—indicates a VLAN priority tag detected with received packet. [19:16]:rx_w_tci [3:0]—indicates VLAN priority of received packet. [15]:rx_w_vlan_tagged—indicates VLAN tag detected with received packet. [14]:rx_w_bad_frame—indicates received packet is bad, or the FIFO has overflowed. [13:0]: rx_w_frame_length—indicates number of bytes in received packet.
enet0_rx_w_err	O	Error, active-High output indicating the current packet contains error. This signal is only valid when both rx_w_wr and rx_w_eop are active-High. Rx_w_err is also set if the frame has not been matched by one of the filters.
enet0_rx_w_overflow	I	FIFO overflow. Indicates to the Ethernet MAC that the external RX FIFO has overflowed. The Ethernet MAC uses this signal for status reporting at the end of frame (EOF).
enet0_rx_w_flush	O	FIFO flush, active-High output indicating that the external RX FIFO must be cleared of all data.

Table B-6: FIFO_ENET1
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
enet1_tx_r_data_rdy	I	When set to logic 1. Indicates enough data is present in the external FIFO for Ethernet frame transmission to commence on the current packet.
enet1_tx_r_rd	O	Single tx_clk clock cycle wide active-High output requesting a 32-bit word of information from the external FIFO interface. Synchronous to the tx_clk clock domain.
enet1_tx_r_valid	I	Single tx_clk clock cycle wide active-High input indicating requested FIFO data is now valid. Validates the following inputs: tx_r_data[31:0], tx_r_sop, tx_r_eop, tx_r_err and tx_r_mod[1:0].
enet1_tx_r_data	I	FIFO data for transmission. This output is only valid while tx_r_valid is High.
enet1_tx_r_sop	I	Start of packet. Indicates the word received from the external FIFO interface is the first in a packet. This input is only valid while tx_r_valid is High.
enet1_tx_r_eop	I	End of packet. Indicates the word received from the external FIFO interface is the last in a packet. This input is only valid while tx_r_valid is High.
enet1_tx_r_err	I	Error, active-High input indicating the current packet contains an error. This signal is only valid while tx_r_valid is High and can be set at any time during the packet transfer.
enet1_tx_r_underflow	I	FIFO underflow. Indicates the transmit FIFO was empty when a read was attempted. This signal is only valid when a read has been attempted and the tx_r_valid signal has not yet been received.
enet1_tx_r_flushed	I	FIFO flush in progress. Indicates the transmit FIFO is currently removing any residue data content.
enet1_tx_r_control	I	tx_no_crc, set active-High at SOP to indicate current frame is to be transmitted without crc being appended. This input is only valid while both tx_r_valid and tx_r_sop are High.
enet1_dma_tx_end_tog	O	Toggled to indicate that a frame has been completed and status is now valid on the tx_r_status output. Note that this signal is not activated when a frame is being retired due to a collision.
enet1_dma_tx_status_tog	I	This signal must be toggled each time either tx_end_tog or collision_occured are activated. Indicates that the status has been acknowledged.
enet1_tx_r_status	O	[3]: fifo_underrun—status output indicating that the Ethernet MAC transmitter has underrun due to one of the following conditions. Data under run indicated by tx_r_underflow input from the external FIFO interface during the last frame transfer. Reset once efifo_tx_status_tog changes logic state. [2]:collision_occured—status output Indicating that the frame in progress has suffered a collision and that re-transmission of the frame should take place. [1]: late_coll_occured—status output indicating that the frame in progress suffered a late collision and can be optionally retired. [0]:too_many_retires—status output indicating the frame in progress experienced excess collisions and was aborted.
enet1_rx_w_wr	O	Single rx_clk clock cycle wide active-High output indicating a write to the external FIFO interface.
enet1_rx_w_data	O	Received data for output to the external FIFO interface. This output is only when rx_w_wr is High.
enet1_rx_w_sop	O	Start of packet. Indicates the word output to the external FIFO interface is the first in a packet. This output is only valid when rx_w_wr is High.
enet1_rx_w_eop	O	End of packet. Indicates the word output to the external FIFO interface is the last in a packet. This output is only valid when rx_w_wr is High.
enet1_rx_w_status	O	Status signals, valid when rx_w_eop is High and rx_w_err is Low, otherwise driven to zero. [29]:Rx_w_type_match—indicates the received frame was matched on type ID register. [28]:rx_w_add_match4—indicates the received frame was matched on specific address register4. [27]:rx_w_add_match3—indicates the received frame was matched on specific address register3. [26]:rx_w_add_match3—indicates the received frame was matched on specific address register2. [25]:rx_w_add_match3—indicates the received frame was matched on specific address register1. [24]:rx_w_ext_match—indicates the received frame was matched externally by the eam input pin. [23]:rx_w_uni_hash_match—indicates the received frame was matched as a unicast hash frame. [22]:rx_w_mult_hash_match—indicates the received frame was matched as a multicast hash frame. [21]:rx_w_broadcast_frame—indicates the received frame is a broadcast frame. [20]:rx_w_prty_tagged—indicates a VLAN priority tag detected with received packet. [19:16]:rx_w_tci [3:0]—indicates VLAN priority of received packet. [15]:rx_w_vlan_tagged—indicates VLAN tag detected with received packet. [14]:rx_w_bad_frame—indicates received packet is bad or the FIFO has overflowed. [13:0]: rx_w_frame_length—indicates number of bytes in received packet.
enet1_rx_w_err	O	Error, active-High output indicating the current packet contains an error. This signal is only valid when both rx_w_wr and rx_w_eop are active-High. rx_w_err is also set if the frame has not been matched by one of the filters.
enet1_rx_w_overflow	I	FIFO overflow. Indicates to the Ethernet MAC that the external RX FIFO has overflowed. The Ethernet MAC uses this signal for status reporting at the EOF.
enet1_rx_w_flush	O	FIFO flush, active-High output indicating that the external RX FIFO must be cleared of all data.

Table B-7: FIFO_ENET2
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
enet2_tx_r_data_rdy	I	When set to logic 1. Indicates enough data is present in the external FIFO for Ethernet frame transmission to commence on the current packet.
enet2_tx_r_rd	O	Single tx_clk clock cycle wide active-High output requesting a 32-bit word of information from the external FIFO interface. Synchronous to the tx_clk clock domain.
enet2_tx_r_valid	I	Single tx_clk clock cycle wide active-High input indicating requested FIFO data is now valid. Validates the following inputs: tx_r_data[31:0], tx_r_sop, tx_r_eop, tx_r_err and tx_r_mod[1:0].
enet2_tx_r_data	I	FIFO data for transmission. This output is only valid while tx_r_valid is High.
enet2_tx_r_sop	I	Start of packet. Indicates the word received from the external FIFO interface is the first in a packet. This input is only valid while tx_r_valid is High.
enet2_tx_r_eop	I	End of packet. Indicates the word received from the external FIFO interface is the last in a packet. This input is only valid while tx_r_valid is High.
enet2_tx_r_err	I	Error. Active-High input indicating the current packet contains an error. This signal is only valid while tx_r_valid is High and can be set at any time during the packet transfer.
enet2_tx_r_underflow	I	FIFO underflow. Indicates the transmit FIFO was empty when a read was attempted. This signal is only valid when a read has been attempted and the tx_r_valid signal has not yet been received.
enet2_tx_r_flushed	I	FIFO flush in progress. Indicates the transmit FIFO is currently removing any residue data content.
enet2_tx_r_control	I	tx_no_crc. Set active-High at SOP to indicate current frame is to be transmitted without crc being appended. This input is only valid while both tx_r_valid and tx_r_sop are High.
enet2_dma_tx_end_tog	O	Toggled to indicate that a frame has been completed and status is now valid on the tx_r_status output. Note that this signal is not activated when a frame is being retired due to a collision.
enet2_dma_tx_status_tog	I	This signal must be toggled each time either tx_end_tog or collision_occured are activated. Indicates that the status has been acknowledged.
enet2_tx_r_status	O	[3]: fifo_underrun—status output indicating that the Ethernet MAC transmitter has under run due to one of the following conditions. Data under run indicated by tx_r_underflow input from the external FIFO interface during the last frame transfer. Reset once efifo_tx_status_tog changes logic state. [2]:collision_occured—status output Indicating that the frame in progress has suffered a collision and that re-transmission of the frame should take place. [1]: late_coll_occured—status output indicating that the frame in progress suffered a late collision and can be optionally retired. [0]:too_many_retires—status output indicating the frame in progress experienced excess collisions and was aborted.
enet2_rx_w_wr	O	Single rx_clk clock cycle wide active-High output indicating a write to the external FIFO interface.
enet2_rx_w_data	O	Received data for output to the external FIFO interface. This output is only when rx_w_wr is High.
enet2_rx_w_sop	O	Start of packet. Indicates the word output to the external FIFO interface is the first in a packet. This output is only valid when rx_w_wr is High.
enet2_rx_w_eop	O	End of packet. Indicates the word output to the external FIFO interface is the last in a packet. This output is only valid when rx_w_wr is High.
enet2_rx_w_status	O	Status signals. Valid when rx_w_eop is High and rx_w_err is Low, otherwise driven to zero. [29]:Rx_w_type_match—indicates the received frame was matched on type ID register [28]:rx_w_add_match4—indicates the received frame was matched on specific address register4 [27]:rx_w_add_match3—indicates the received frame was matched on specific address register3. [26]:rx_w_add_match3—indicates the received frame was matched on specific address register2. [25]:rx_w_add_match3—indicates the received frame was matched on specific address register1. [24]:rx_w_ext_match—indicates the received frame was matched externally by the eam input pin. [23]:rx_w_uni_hash_match—indicates the received frame was matched as a unicast hash frame. [22]:rx_w_mult_hash_match—indicates the received frame was matched as a multicast hash frame. [21]:rx_w_broadcast_frame—indicates the received frame is a broadcast frame. [20]:rx_w_prty_tagged—indicates a VLAN priority tag detected with received packet. [19:16]:rx_w_tci [3:0]—indicates VLAN priority of received packet. [15]:rx_w_vlan_tagged—indicates VLAN tag detected with received packet. [14]:rx_w_bad_frame—indicates received packet is bad, or the FIFO has overflowed. [13:0]: rx_w_frame_length—indicates number of bytes in received packet.
enet2_rx_w_err	O	Error, active-High output indicating the current packet contains error. This signal is only valid when both rx_w_wr and rx_w_eop are active-High. Rx_w_err is also set if the frame has not been matched by one of the filters.
enet2_rx_w_overflow	I	FIFO overflow. Indicates to the Ethernet MAC that the external RX FIFO has overflowed. The Ethernet MAC uses this signal for status reporting at the EOF.
enet2_rx_w_flush	O	FIFO flush, active-High output indicating that the external RX FIFO must be cleared of all data.

Table B-8: FIFO_ENET3
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
enet3_tx_r_data_rdy	I	When set to logic 1, indicates enough data is present in the external FIFO for Ethernet frame transmission to commence on the current packet.
enet3_tx_r_rd	O	Single tx_clk clock cycle wide. Active-High output requesting a 32-bit word of information from the external FIFO interface. Synchronous to the tx_clk clock domain.
enet3_tx_r_valid	I	Single tx_clk clock cycle wide. Active-High input indicating requested FIFO data is now valid. Validates the following inputs: tx_r_data[31:0], tx_r_sop, tx_r_eop, tx_r_err and tx_r_mod[1:0]
enet3_tx_r_data	I	FIFO data for transmission. This output is only valid while tx_r_valid is High.
enet3_tx_r_sop	I	Start of packet. Indicates the word received from the external FIFO interface is the first in a packet. This input is only valid while tx_r_valid is High.
enet3_tx_r_eop	I	End of packet. Indicates the word received from the external FIFO interface is the last in a packet. This input is only valid while tx_r_valid is High.
enet3_tx_r_err	I	Error. Active-High input indicating the current packet contains an error. This signal is only valid while tx_r_valid is High and can be set at any time during the packet transfer.
enet3_tx_r_underflow	I	FIFO underflow. Indicates the transmit FIFO was empty when a read was attempted. This signal is only valid when a read has been attempted and the tx_r_valid signal has not yet been received.
enet3_tx_r_flushed	I	FIFO flush in progress. Indicates the transmit FIFO is currently removing any residue data content.
enet3_tx_r_control	I	tx_no_crc. Set active-High at SOP to indicate current frame is to be transmitted without crc being appended. This input is only valid while both tx_r_valid and tx_r_sop are High.
enet3_dma_tx_end_tog	O	Toggled to indicate that a frame has been completed and status is now valid on the tx_r_status output. Note that this signal is not activated when a frame is being retired due to a collision.
enet3_dma_tx_status_tog	I	This signal must be toggled each time either tx_end_tog or collision_occured are activated. Indicates that the status has been acknowledged.
enet3_tx_r_status	O	[3]: fifo_underrun—status output indicating that the Ethernet MAC transmitter has under-run due to one of the following conditions. Data under run indicated by tx_r_underflow input from the external FIFO interface during the last frame transfer. Reset once efifo_tx_status_tog changes logic state. [2]:collision_occured—status output Indicating that the frame in progress has suffered a collision and that re-transmission of the frame should take place. [1]: late_coll_occured—status output indicating that the frame in progress suffered a late collision and can be optionally retired. [0]:too_many_retires—status output indicating the frame in progress experienced excess collisions and was aborted.
enet3_rx_w_wr	O	Single rx_clk clock cycle wide active-High output indicating a write to the external FIFO interface.
enet3_rx_w_data	O	Received data for output to the external FIFO interface. This output is only when rx_w_wr is High.
enet3_rx_w_sop	O	Start of packet. Indicates the word output to the external FIFO interface is the first in a packet. This output is only valid when rx_w_wr is High.
enet3_rx_w_eop	O	End of packet. Indicates the word output to the external FIFO interface is the last in a packet. This output is only valid when rx_w_wr is High.
enet3_rx_w_status	O	Status signals. Valid when rx_w_eop is High and rx_w_err is Low, otherwise driven to zero. [29]:Rx_w_type_match—indicates the received frame was matched on type ID register. [28]:rx_w_add_match4—indicates the received frame was matched on specific address register4. [27]:rx_w_add_match3—indicates the received frame was matched on specific address register3. [26]:rx_w_add_match3—indicates the received frame was matched on specific address register2. [25]:rx_w_add_match3—indicates the received frame was matched on specific address register1. [24]:rx_w_ext_match—indicates the received frame was matched externally by the eam input pin. [23]:rx_w_uni_hash_match—indicates the received frame was matched as a unicast hash frame. [22]:rx_w_mult_hash_match—indicates the received frame was matched as a multicast hash frame. [21]:rx_w_broadcast_frame—indicates the received frame is a broadcast frame. [20]:rx_w_prty_tagged—indicates a VLAN priority tag detected with received packet. [19:16]:rx_w_tci [3:0]—indicates VLAN priority of received packet. [15]:rx_w_vlan_tagged—indicates VLAN tag detected with received packet. [14]:rx_w_bad_frame—indicates received packet is bad, or the FIFO has overflowed. [13:0]: rx_w_frame_length—indicates number of bytes in received packet.
enet3_rx_w_err	O	Error. Active-High output indicating the current packet contains error. This signal is only valid when both rx_w_wr and rx_w_eop are active-High. Rx_w_err is also set if the frame has not been matched by one of the filters.
enet3_rx_w_overflow	I	FIFO overflow. Indicates to the Ethernet MAC that the external RX FIFO has overflowed. The Ethernet MAC uses this signal for status reporting at the EOF.
enet3_rx_w_flush	O	FIFO flush, active-High output indicating that the external RX FIFO must be cleared of all data.

Table B-9: FTM
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
pl_ps_trigack	I	Trigger acknowledgement from PL
pl_ps_trigger	O	Trigger output to PL
ps_pl_trigack	O	Trigger acknowledgement to PL
ps_pl_trigger	I	Trigger input from PL
gpo	O	General purpose output
gpi	I	General purpose input

Table B-10: TSU
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
emio_enetx_tsu_inc_ctrl	I	TSU increment control
fmio_gem_tsu_clk_from_pl	I	TSU clock source from PL
emio_enetx_tsu_timer_cmp_val	O	TSU timer compare value
emio_enet0_enet_tsu_timer_cnt	O	TSU timer count value

Table B-11: GMII_ENET0
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
enet0_gmii_rx_clk	I	GEM 0 Receive clock to the system clock generator
enet0_speed_mode	O	Indicates speed and external interface that the GEM is currently configured to use to the system clock generator
enet0_gmii_crs	I	Carrier sense from the PHY
enet0_gmii_col	I	Collision detect from the PHY
enet0_gmii_rxd	I	Receive data from the PHY
enet0_gmii_rx_er	I	Receive error signal from the PHY
enet0_gmii_rx_dv	I	Receive data valid signal from the PHY
enet0_gmii_tx_clk	I	GEM 0 Transmit clock from the system clock generator
enet0_gmii_txd	O	Transmit data to the PHY
enet0_gmii_tx_en	O	Transmit enable to the PHY
enet0_gmii_tx_er	O	Transmit error signal to the PHY. Asserted if the DMA block fails to fetch data from memory during frame transmission.

Table B-12: GMII_ENET1
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
enet1_gmii_rx_clk	I	GEM 1 Receive clock to the system clock generator
enet1_speed_mode	O	Indicates speed and external interface that the GEM is currently configured to use to the system clock generator
enet1_gmii_crs	I	Carrier sense from the PHY
enet1_gmii_col	I	Collision detect from the PHY
enet1_gmii_rxd	I	Receive data from the PHY
enet1_gmii_rx_er	I	Receive error signal from the PHY
enet1_gmii_rx_dv	I	Receive data valid signal from the PHY
enet1_gmii_tx_clk	I	GEM 1 Transmit clock from the system clock generator
enet1_gmii_txd	O	Transmit data to the PHY
enet1_gmii_tx_en	O	Transmit enable to the PHY
enet1_gmii_tx_er	O	Transmit error signal to the PHY. Asserted if the DMA block fails to fetch data from memory during frame transmission

Table B-13: GMII_ENET2
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
enet2_gmii_rx_clk	I	GEM 2 Receive clock to the system clock generator
enet2_speed_mode	O	Indicates speed and external interface that the GEM is currently configured to use to the system clock generator
enet2_gmii_crs	I	Carrier sense from the PHY
enet2_gmii_col	I	Collision detect from the PHY
enet2_gmii_rxd	I	Receive data from the PHY
enet2_gmii_rx_er	I	Receive error signal from the PHY
enet2_gmii_rx_dv	I	Receive data valid signal from the PHY
enet2_gmii_tx_clk	I	GEM 3 Transmit clock from the system clock generator
enet2_gmii_txd	O	Transmit data to the PHY
enet2_gmii_tx_en	O	Transmit enable to the PHY
enet2_gmii_tx_er	O	Transmit error signal to the PHY. Asserted if the DMA block fails to fetch data from memory during frame transmission.

Table B-14: GMII_ENET3
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
enet3_gmii_rx_clk	I	GEM 3 Receive clock to the system clock generator
enet3_speed_mode	O	Indicates speed and external interface that the GEM is currently configured to use to the system clock generator.
enet3_gmii_crs	I	Carrier sense from the PHY
enet3_gmii_col	I	Collision detect from the PHY
enet3_gmii_rxd	I	Receive data from the PHY
enet3_gmii_rx_er	I	Receive error signal from the PHY
enet3_gmii_rx_dv	I	Receive data valid signal from the PHY
enet3_gmii_tx_clk	I	GEM 3 Transmit clock from the system clock generator
enet3_gmii_txd	O	Transmit data to the PHY
enet3_gmii_tx_en	O	Transmit enable to the PHY
enet3_gmii_tx_er	O	Transmit error signal to the PHY. Asserted if the DMA block fails to fetch data from memory during frame transmission.

Table B-15: GPIO_0
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
gpio_i	I	GPIO port input
gpio_o	O	GPIO port output
gpio_t	O	3-state enable signal for GPIO port

Table B-16: IIC0
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
i2c0_scl_i	I	Actual state of the external serial clock (SCL) clock signal
i2c0_scl_o	O	Clock level to be placed on SCL pin
i2c0_scl_t	O	3-state enable for the SCL output buffer. This signal has a direct connection to i2c0_scl_oe.
i2c0_sda_i	I	Actual state of the external serial data (SDA) signal
i2c0_sda_o	O	Data bit to be placed on external SDA signal
i2c0_sda_t	O	3-state enable for the SDA output buffer This signal has a direct connection to i2c0_sda_oe.

Table B-17: IIC1
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
i2c1_scl_i	I	Actual state of the external SCL clock signal
i2c1_scl_o	O	Clock level to be placed on SCL pin
i2c1_scl_t	O	3-state enable for the SCL output buffer. This signal has a direct connection to i2c1_scl_oe.
i2c1_sda_i	I	Actual state of the external SDA signal
i2c1_sda_o	O	Data bit to be placed on external SDA signal
i2c1_sda_t	O	3-state enable for the SDA output buffer. This signal has a direct connection to i2c1_sda_oe.

Table B-18: MDIO_ENET0
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
enet0_mdio_mdc	O	Management data clock to pin
enet0_mdio_i	I	Management data input from MDIO pin
enet0_mdio_o	O	Management data output to MDIO pin
enet0_mdio_t	O	3-state enable to MDIO pin, active-Low. At the top-level the three MDIO pins are all used to drive a single 3-state pin.

Table B-19: MDIO_ENET1
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
enet1_mdio_mdc	O	Management data clock to pin
enet1_mdio_i	I	Management data input from MDIO pin
enet1_mdio_o	O	Management data output to MDIO pin
enet1_mdio_t	O	3-state enable to MDIO pin, active-Low. At the top-level the three MDIO pins are all used to drive a single 3-state pin.

Table B-20: MDIO_ENET2
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
enet2_mdio_mdc	O	Management data clock to pin
enet2_mdio_i	I	Management data input from MDIO pin
enet2_mdio_o	O	Management data output to MDIO pin
enet2_mdio_t	O	3-state enable to MDIO pin, active-Low. At the top-level the three MDIO pins are all used to drive a single 3-state pin.

Table B-21: MDIO_ENET3
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
enet3_mdio_mdc	O	Management data clock to pin
enet3_mdio_i	I	Management data input from MDIO pin
enet3_mdio_o	O	Management data output to MDIO pin
enet3_mdio_t	O	3-state enable to MDIO pin, active-Low. At the top-level the three MDIO pins are all used to drive a single 3-state pin.

Table B-22: PL_CLK0
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
pl_clk0	O	PL Clock 0

Table B-23: PL_CLK1
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
pl_clk1	O	PL Clock 1

Table B-24: PL_CLK2
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
pl_clk2	O	PL Clock 2

Table B-25: PL_CLK3
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
pl_clk3	O	PL Clock 3

Table B-26: PL_PS_IRQ0
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
pl_ps_irq0	I	pl to ps interrupt 0

Table B-27: PL_PS_IRQ1
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
pl_ps_irq1	I	pl to ps interrupt 1

Table B-28: SDIO0
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
sdio0_clkout	O	Clock output to SD/SDIO0 slave device
sdio0_fb_clk_in	I	Clock feedback from sd0_clk_out from pad
sdio0_cmdout	O	Command indicator output
sdio0_cmdin	I	Command indicator input
sdio0_cmdena	O	Command indicator enable
sdio0_datain	I	7-bit input data bus. Can also be used in SPI flash memory, serial or 2-bit modes.
sdio0_dataout	O	7-bit output data bus. Can also be used in SPI flash memory, serial or 2-bit modes.
sdio0_dataena	O	Enable control for data bus
sdio0_cd_n	I	Card detection for single slot
sdio0_wp	I	Secure digital non-volatile memory card (SD card) write protect, active-Low
sdio0_ledcontrol	O	LED ON. Cautions you not to remove the card while the SD card is being accessed.
sdio0_buspower	O	Control SD card power supply
sdio0_bus_volt	O	SD bus volt select

Table B-29: SDIO1
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
sdio1_clkout	O	Clock output to SD/SDIO1 slave device
sdio1_fb_clk_in	I	Clock feedback from sd1_clk_out from pad
sdio1_cmdout	O	Command indicator output
sdio1_cmdin	I	Command indicator input
sdio1_cmdena	O	Command indicator enable
sdio1_datain	I	7-bit input data bus. Can also be used in SPI flash memory, serial or 2-bit modes.
sdio1_dataout	O	7-bit output data bus. Can also be used in SPI flash memory, serial or 2-bit modes.
sdio1_dataena	O	Enable control for data bus
sdio1_cd_n	I	Card detection for single slot
sdio1_wp	I	SD card write protect, active-Low
sdio1_ledcontrol	O	LED ON: Cautions you not to remove the card while the SD card is being accessed.
sdio1_bus_power	O	Control SD card power supply
sdio1_bus_volt	O	SD bus volt select

Table B-30: SPI0
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
spi0_sclk_i	I	SPI flash memory slave clock
spi0_sclk_o	O	SPI flash memory master clock output
spi0_sclk_t	O	SPI flash memory clock 3-state enable, active-Low. This signal is a version of spi0_n_sclk_en.
spi0_m_i	I	SPI flash memory master in slave out (MISO) signal, master input
spi0_m_o	O	SPI flash memory master out slave in (MOSI) signal, master output
spi0_mo_t	O	SPI flash memory MOSI signal, 3-state enable, active-Low. This signal is a version of spi0_n_mo_en.
spi0_s_i	I	SPI flash memory MOSI signal, slave input
spi0_s_o	O	SPI flash memory MISO signal, slave output
spi0_n_ss_o_n	O	SPI flash memory slave select outputs
spi0_ss_n_t	O	SPI flash memory slave select 3-state enable, active-Low. This signal is a version of spi0_n_ss_en.

Table B-31: SPI1
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
spi1_sclk_i	I	SPI flash memory slave clock. Can be passed directly from pin if low speed (< 50 MHz).
spi1_sclk_o	O	SPI flash memory master clock output. Can be passed directly to pin if low speed (< 50 MHz).
spi1_sclk_t	O	SPI flash memory clock 3-state enable, active-Low. This signal is a version of spi1_n_sclk_en
spi1_m_i	I	SPI flash memory MISO signal, master input
spi1_m_o	O	SPI flash memory MOSI signal, master output
spi1_mo_t	O	SPI flash memory MOSI signal, 3-state enable, active-Low. This signal is a version of spi1_n_mo_en.
spi1_s_i	I	SPI flash memory MOSI signal, slave input
spi1_s_o	O	SPI flash memory MISO signal, slave output
spi1_n_ss_o_n	O	SPI flash memory peripheral select outputs
spi1_ss_n_t	O	SPI flash memory slave select 3-state enable, active-Low. This signal is a version of spi1_n_ss_en.

Table B-32: Trace0
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
tracectl	O	Trace control
tracedata	O	Trace data

Table B-33: UART0
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
uart0_ctsn	I	Clear-to-send flow control
uart0_rtsn	O	Request-to-send flow control
uart0_dsrn	I	Modem data set ready
uart0_dcdn	I	Modem data carrier detect
uart0_rin	I	Modem ring indicator
uart0_dtrn	O	Modem data terminal ready

Table B-34: UART1
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
uart1_ctsn	I	Clear-to-send flow control
uart1_rtsn	O	Request-to-send flow control
uart1_dsrn	I	Modem data set ready
uart1_dcdn	I	Modem data carrier detect
uart1_rin	I	Modem ring indicator
uart1_dtrn	O	Modem data terminal ready

Table B-35: TTC0
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
ttc0_wave_o	O	Triple timer counter (TTC) clock (Waveform generated)
ttc0_clk_i	I	TTC0 clock input

Table B-36: TTC1
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
ttc1_wave_o	O	TTC clock (Waveform generated)
ttc1_clk_i	I	TTC1 clock input

Table B-37: TTC2
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
ttc3_wave_o	O	TTC clock (Waveform generated)
ttc2_clk_i	I	TTC2 clock input

Table B-38: TTC3
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
ttc3_wave_o	O	TTC clock (Waveform generated)
ttc3_clk_i	I	TTC3 clock input

Table B-39: WDT0
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
wdt0_clk_i	I	WDT0 clock input
wdt0_rst_o	O	WDT0 reset

Table B-40: WDT1
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
wdt1_clk_i	I	WDT1 clock input
wdt1_rst_o	O	WDT1 reset

Table B-41: Interrupt Signals
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
ps_pl_irq_can0	O	CAN0 interrupt
ps_pl_irq_can1	O	CAN1 interrupt
ps_pl_irq_enet0	O	Ethernet0 interrupt
ps_pl_irq_enet1	O	Gigabit ethernet1 interrupt
ps_pl_irq_enet2	O	Gigabit ethernet2 interrupt
ps_pl_irq_enet3	O	Gigabit ethernet3 interrupt
ps_pl_irq_enet0_wake0	O	Ethernet0 wake-up interrupt
ps_pl_irq_enet0_wake1	O	Gigabit ethernet1 wake-up interrupt
ps_pl_irq_enet0_wake2	O	Gigabit ethernet2 wake-up interrupt
ps_pl_irq_enet0_wake3	O	Gigabit ethernet3 wake-up interrupt
ps_pl_irq_gpio	O	GPIO interrupt
ps_pl_irq_i2c0	O	I2C0 interrupt
ps_pl_irq_i2c1	O	I2C1 interrupt
ps_pl_irq_uart0	O	UART0 interrupt
ps_pl_irq_uart1	O	UART1 interrupt
ps_pl_irq_sdio0	O	SDIO0 interrupt
ps_pl_irq_sdio1	O	SDIO1 interrupt
ps_pl_irq_sdio0_wake	O	SDIO0 wake interrupt
ps_pl_irq_sdio1_wake	O	SDIO1 wake interrupt
ps_pl_irq_spi0	O	SPI0 interrupt
ps_pl_irq_spi1	O	SPI1 interrupt
ps_pl_irq_qspi	O	SPI flash memory interrupt
ps_pl_irq_ttc0_0	O	Triple Timer 0 Counter 0 Interrupt
ps_pl_irq_ttc0_1	O	Triple Timer 0 Counter 1 Interrupt
ps_pl_irq_ttc0_2	O	Triple Timer 0 Counter 2 Interrupt
ps_pl_irq_ttc1_0	O	Triple Timer 1 Counter 0 Interrupt
ps_pl_irq_ttc1_1	O	Triple Timer 1 Counter 1 Interrupt
ps_pl_irq_ttc1_2	O	Triple Timer 1 Counter 2 Interrupt
ps_pl_irq_ttc2_0	O	Triple Timer 2 Counter 0 Interrupt

Table B-42: M_AXI_HPM0_FPD
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
maxigp0_awid	O	Write address ID. This signal is the identification tag for the write address group of signals.
maxigp0_awaddr	O	Write address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
maxigp0_awlen	O	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
maxigp0_awsize	O	Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
maxigp0_awburst	O	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
maxigp0_awlock	O	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
maxigp0_awcache	O	Cache type. This signal indicates the bufferable, cacheable, write-through, write-back, and allocate attributes of the transaction.
maxigp0_awprot	O	Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
maxigp0_awvalid	O	Write address valid. This signal indicates that valid write address and control information are available. 1 = address and control information available 0 = address and control information not available The address and control information remain stable until the address acknowledge signal, AWREADY, goes High.
maxigp0_awuser	O	User-defined address write (AW) channel signals
maxigp0_awready	I	Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready
maxigp0_wdata	O	Write data. The write data bus can be 32, 64, or 128 bits wide.
maxigp0_wstrb	O	Write strobes. This signal indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
maxigp0_wlast	O	Write last. This signal indicates the last transfer in a write burst.
maxigp0_wvalid	O	Write valid. This signal indicates that valid write data and strobes are available. 1 = write data and strobes available 0 = write data and strobes not available
maxigp0_wready	I	Write ready. This signal indicates that the slave can accept the write data. 1 = slave ready 0 = slave not ready
maxigp0_bid	I	Response ID. The identification tag of the write response
maxigp0_bresp	I	Write response. This signal indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
maxigp0_bvalid	I	Write response valid. This signal indicates that a valid write response is available. 1 = write response available 0 = write response not available
maxigp0_bready	O	Response ready. This signal indicates that the master can accept the response information. 1 = master ready 0 = master not ready
maxigp0_arid	O	Read address ID. This signal is the identification tag for the read address group of signals.
maxigp0_araddr	O	Read address. The read address bus gives the initial address of a read burst transaction.
maxigp0_arlen	O	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
maxigp0_arsize	O	Burst size. This signal indicates the size of each transfer in the burst
maxigp0_arburst	O	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
maxigp0_arlock	O	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
maxigp0_arcache	O	Cache type. This signal provides additional information about the cacheable characteristics of the transfer
maxigp0_arprot	O	Protection type. This signal provides protection unit information for the transaction.
maxigp0_arvalid	O	Read address valid. This signal indicates, when High, that the read address and control information is valid and remains stable until the address acknowledge signal, ARREADY, is High.
maxigp0_aruser	O	User-defined address read (AR) channel signals
maxigp0_arready	I	Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready
maxigp0_rid	I	Read ID tag. This signal is the ID tag of the read data group of signals.
maxigp0_rdata	I	Read data. The read data bus can be 8, 16, 32, 64, 128, 256, 512, or 1,024 bits wide.
maxigp0_rresp	I	Read response. This signal indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
maxigp0_rlast	I	Read last. This signal indicates the last transfer in a read burst.
maxigp0_rvalid	I	Read valid. This signal indicates that the required read data is available and the read transfer can complete.
maxigp0_rready	O	Read ready. This signal indicates that the master can accept the read data and response information. 1= master ready 0 = master not ready
maxigp0_awqos	O	Wr addr channel quality of service (QOS) input
maxigp0_arqos	O	Rd addr channel QOS input

Table B-43: M_AXI_HPM0_FPD_ACLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
maxigp0_awid	O	Write address ID. This signal is the identification tag for the write address group of signals.
maxihpm0_fpd_aclk	I	Input clock signal

Table B-44: M_AXI_HPM0_LPD
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
maxigp2_awid	O	Write address ID. This signal is the identification tag for the write address group of signals.
maxigp2_awaddr	O	Write address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
maxigp2_awlen	O	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
maxigp2_awsize	O	Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
maxigp2_awburst	O	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
maxigp2_awlock	O	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
maxigp2_awcache	O	Cache type. This signal indicates the buffer able, cacheable, write-through, write-back, and allocate attributes of the transaction.
maxigp2_awprot	O	Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
maxigp2_awvalid	O	Write address valid. This signal indicates that valid write address and control information are available. 1 = address and control information available 0 = address and control information not available The address and control information remain stable until the address acknowledge signal, AWREADY, goes High.
maxigp2_awuser	O	User-defined address write (AW) channel signals
maxigp2_awready	I	Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready
maxigp2_wdata	O	Write data. The write data bus can be 32, 64, or 128 bits wide.
maxigp2_wstrb	O	Write strobes. This signal indicates which byte lanes to update in memory. There is one write strobe for each 8 bits of the write data bus.
maxigp2_wlast	O	Write last. This signal indicates the last transfer in a write burst.
maxigp2_wvalid	O	Write valid. This signal indicates that valid write data and strobes are available. 1 = write data and strobes available 0 = write data and strobes not available
maxigp2_wready	I	Write ready. This signal indicates that the slave can accept the write data. 1 = slave ready 0 = slave not ready
maxigp2_bid	I	Response ID. The identification tag of the write response
maxigp2_bresp	I	Write response. This signal indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
maxigp2_bvalid	I	Write response valid. This signal indicates that a valid write response is available. 1 = write response available 0 = write response not available
maxigp2_bready	O	Response ready. This signal indicates that the master can accept the response information. 1 = master ready 0 = master not ready
maxigp2_arid	O	Read address ID. This signal is the identification tag for the read address group of signals.
maxigp2_araddr	O	Read address. The read address bus gives the initial address of a read burst transaction.
maxigp2_arlen	O	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
maxigp2_arsize	O	Burst size. This signal indicates the size of each transfer in the burst.
maxigp2_arburst	O	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
maxigp2_arlock	O	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
maxigp2_arcache	O	Cache type. This signal provides additional information about the cacheable characteristics of the transfer.
maxigp2_arprot	O	Protection type. This signal provides protection unit information for the transaction.
maxigp2_arvalid	O	Read address valid. This signal indicates, when High, that the read address and control information is valid and remains stable until the address acknowledge signal, ARREADY, is High.
maxigp2_aruser	O	User-defined AR channel signals
maxigp2_arready	I	Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready
maxigp2_rid	I	Read ID tag. This signal is the ID tag of the read data group of signals.
maxigp2_rdata	I	Read data. The read data bus can be 8, 16, 32, 64, 128, 256, 512, or 1,024 bits wide.
maxigp2_rresp	I	Read response. This signal indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR
maxigp2_rlast	I	Read last. This signal indicates the last transfer in a read burst.
maxigp2_rvalid	I	Read valid. This signal indicates that the required read data is available and the read transfer can complete.
maxigp2_rready	O	Read ready. This signal indicates that the master can accept the read data and response information. 1= master ready 0= master not ready
maxigp2_awqos	O	Wr addr channel QOS input
maxigp2_arqos	O	Rd addr channel QOS input

Table B-45: M_AXI_HPM0_LPD_ACLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
maxigp2_awid	O	Write address ID. This signal is the identification tag for the write address group of signals.
maxihpm0_lpd_aclk	I	Input clock signal

Table B-46: M_AXI_HPM1_FPD
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
maxigp1_awid	O	Write address ID. This signal is the identification tag for the write address group of signals.
maxigp1_awaddr	O	Write address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
maxigp1_awlen	O	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
maxigp1_awsize	O	Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
maxigp1_awburst	O	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
maxigp1_awlock	O	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
maxigp1_awcache	O	Cache type. This signal indicates the buffer able, cacheable, write-through, write-back, and allocate attributes of the transaction.
maxigp1_awprot	O	Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
maxigp1_awvalid	O	Write address valid. This signal indicates that valid write address and control information are available. 1 = address and control information available 0 = address and control information not available The address and control information remain stable until the address acknowledge signal, AWREADY, goes High.
maxigp1_awuser	O	User-defined AW channel signals
maxigp1_awready	I	Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready
maxigp1_wdata	O	Write data. The write data bus can be 32, 64, or 128 bits wide.
maxigp1_wstrb	O	Write strobes. This signal indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
maxigp1_wlast	O	Write last. This signal indicates the last transfer in a write burst.
maxigp1_wvalid	O	Write valid. This signal indicates that valid write data and strobes are available. 1 = write data and strobes available 0 = write data and strobes not available
maxigp1_wready	I	Write ready. This signal indicates that the slave can accept the write data. 1 = slave ready 0 = slave not ready
maxigp1_bid	I	Response ID. The identification tag of the write response
maxigp1_bresp	I	Write response. This signal indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
maxigp1_bvalid	I	Write response valid. This signal indicates that a valid write response is available. 1 = write response available 0 = write response not available
maxigp1_bready	O	Response ready. This signal indicates that the master can accept the response information. 1 = master ready 0 = master not ready
maxigp1_arid	O	Read address ID. This signal is the identification tag for the read address group of signals.
maxigp1_araddr	O	Read address. The read address bus gives the initial address of a read burst transaction.
maxigp1_arlen	O	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
maxigp1_arsize	O	Burst size. This signal indicates the size of each transfer in the burst.
maxigp1_arburst	O	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
maxigp1_arlock	O	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
maxigp1_arcache	O	Cache type. This signal provides additional information about the cacheable characteristics of the transfer.
maxigp1_arprot	O	Protection type. This signal provides protection unit information for the transaction.
maxigp1_arvalid	O	Read address valid. This signal indicates, when High, that the read address and control information is valid and remains stable until the address acknowledge signal, ARREADY, is High.
maxigp1_aruser	O	User-defined AR channel signals
maxigp1_arready	I	Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready
maxigp1_rid	I	Read ID tag. This signal is the ID tag of the read data group of signals.
maxigp1_rdata	I	Read data. The read data bus can be 8, 16, 32, 64, 128, 256, 512, or 1,024 bits wide.
maxigp1_rresp	I	Read response. This signal indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
maxigp1_rlast	I	Read last. This signal indicates the last transfer in a read burst.
maxigp1_rvalid	I	Read valid. This signal indicates that the required read data is available and the read transfer can complete.
maxigp1_rready	O	Read ready. This signal indicates that the master can accept the read data and response information. 1= master ready 0 = master not ready
maxigp1_awqos	O	Wr addr channel QOS input
maxigp1_arqos	O	Rd addr channel QOS input

Table B-47: M_AXI_HPM1_FPD_ACLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
maxigp1_awid	O	Write address ID. This signal is the identification tag for the write address group of signals.
maxihpm1_fpd_aclk	I	Input clock signal

Table B-48: S_AXI_ACE_FPD
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
sacefpd_wuser	I	User signal. Optional user-defined signal in the write data channel.
sacefpd_buser	O	User signal. Optional user-defined signal in the write response channel.
sacefpd_ruser	O	User signal. Optional user-defined signal in the read data channel.
sacefpd_awuser	I	User signal. Optional user-defined signal in the write address channel.
sacefpd_awsnoop	I	This signal indicates the transaction type for shareable write transactions.
sacefpd_awsize	I	Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
sacefpd_awregion	I	Region identifier. Permits a single physical interface on a slave to be used for multiple logical interfaces.
sacefpd_awqos	I	Quality of service. Identifier sent for each write transaction.
sacefpd_awprot	I	Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
sacefpd_awlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
sacefpd_awid	I	Write address ID. This signal is the identification tag for the write address group of signals.
sacefpd_awdomain	I	The signal indicates the shareability domain of a write transaction.
sacefpd_awcache	I	Cache type. This signal indicates the buffer able, cacheable, write-through, write-back, and allocate attributes of the transaction.
sacefpd_awburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
sacefpd_awbar	I	This signal indicates a write barrier transaction.
sacefpd_awaddr	I	Write address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
sacefpd_awlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
sacefpd_awvalid	I	Write address valid. This signal indicates that valid write address and control information are available. 1 = address and control information available 0 = address and control information not available The address and control information remain stable until the address acknowledge signal, AWREADY, goes High.
sacefpd_awready	O	Write address channel ready signal
sacefpd_wstrb	I	Write strobes. This signal indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
sacefpd_wdata	I	Write data. The write data bus can be 128 bits wide.
sacefpd_wlast	I	Write last. This signal indicates the last transfer in a write burst.
sacefpd_wvalid	I	Write valid. This signal indicates that valid write data and strobes are available. 1 = write data and strobes available 0 = write data and strobes not available
sacefpd_wready	O	Write ready. This signal indicates that the slave can accept the write data. 1 = slave ready 0 = slave not ready
sacefpd_bresp	O	Write response. This signal indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
sacefpd_bid	O	Response ID. The identification tag of the write response
sacefpd_bvalid	O	Write response valid. This signal indicates that a valid write response is available. 1 = write response available 0 = write response not available
sacefpd_bready	I	Response ready. This signal indicates that the master can accept the response information. 1 = master ready 0 = master not ready
sacefpd_aruser	I	User signal. Optional User-defined signal in the read address channel.
sacefpd_arsnoop	I	This signal indicates the transaction type for shareable read transactions.
sacefpd_arsize	I	Burst size. This signal indicates the size of each transfer in the burst.
sacefpd_arregion	I	Region Identifier. Permits a single physical interface on a slave to be used for multiple logical interfaces.
sacefpd_arqos	I	Quality of service, identifier sent for each read transaction.
sacefpd_arprot	I	Protection type. This signal provides protection unit information for the transaction.
sacefpd_arlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
sacefpd_arid	I	Read address ID. This signal is the identification tag for the read address group of signals.
sacefpd_ardomain	I	This signal indicates the shareability domain of a read transaction.
sacefpd_arcache	I	Cache type. This signal provides additional information about the cacheable characteristics of the transfer.
sacefpd_arburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
sacefpd_arbar	I	This signal indicates a read barrier transaction.
sacefpd_araddr	I	Read address. The read address bus gives the initial address of a read burst transaction.
sacefpd_arlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
sacefpd_arvalid	I	Read address valid. This signal indicates, when High, that the read address and control information is valid and remains stable until the address acknowledge signal, ARREADY, is High.
sacefpd_arready	O	Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready
sacefpd_rresp	O	Read response. This signal indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
sacefpd_rid	O	Read ID tag. This signal is the ID tag of the read data group of signals.
sacefpd_rdata	O	Read data. The read data bus can be 8, 16, 32, 64, 128, 256, 512, or 1,024 bits wide.
sacefpd_rlast	O	Read last. This signal indicates the last transfer in a read burst.
sacefpd_rvalid	O	Read valid. This signal indicates that the required read data is available and the read transfer can complete.
sacefpd_rready	I	Read ready. This signal indicates that the master can accept the read data and response information. 1= master ready 0 = master not ready
sacefpd_acsnoop	O	Snoop transaction type. This signal indicates the transaction type of the snoop transaction.
sacefpd_acprot	O	Snoop protection type. This signal indicates the security level of the snoop transaction.
sacefpd_acaddr	O	Snoop Address. This signal indicates the address of a snoop transaction. The snoop address width must match the width of the read and write address buses.
sacefpd_acvalid	O	Snoop address valid. This signal indicates that the snoop address and control information is valid.
sacefpd_acready	I	Snoop address ready. This signal indicates that the snoop address and control information can be accepted in the current cycle.
sacefpd_cddata	I	Snoop data. Transfer data from a snooped master.
sacefpd_cdlast	I	This signal indicates the last data transfer of a snoop transaction.
sacefpd_cdvalid	I	Snoop data valid. This signal indicates that the snoop is valid.
sacefpd_cdready	O	Snoop data ready. This signal indicates that the snoop data can be accepted in the current cycle.
sacefpd_crresp	I	Snoop response. This signal indicates the response to a snoop transaction and how it completes.
sacefpd_crvalid	I	Snoop response valid. This signal indicates that the snoop response is valid.
sacefpd_crready	O	Snoop response ready. This signal indicates the snoop response can be accepted in the current cycle.
sacefpd_wack	I	Write acknowledge. This signal indicates that a master has completed a write transaction.
sacefpd_rack	I	Read acknowledge. This signal indicates that a master has completed a read transaction.

Table B-49: S_AXI_ACP_FPD
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxiacp_awuser	I	User signal. Optional user-defined signal in the write address channel.
saxiacp_buser	O	User signal. Optional user-defined signal in the write response channel.
saxiacp_wuser	I	User signal. Optional user-defined signal in the write data channel.
saxiacp_awid	I	Write address ID. This signal is the identification tag for the write address group of signals.
saxiacp_awaddr	I	Write address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
saxiacp_awlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
saxiacp_awsize	I	Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
saxiacp_awburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
saxiacp_awlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
saxiacp_awcache	I	Cache type. This signal indicates the buffer able, cacheable, write-through, write-back, and allocate attributes of the transaction.
saxiacp_awprot	I	Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
saxiacp_awvalid	I	Write address valid. This signal indicates that valid write address and control information are available. 1 = address and control information available 0 = address and control information not available The address and control information remain stable until the address acknowledge signal, AWREADY, goes High.
saxiacp_awready	I	Write address channel ready signal
saxiacp_wdata	I	Write data. The write data bus can be 128 bits wide.
saxiacp_wstrb	I	Write strobes. This signal indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
saxiacp_wlast	I	Write last. This signal indicates the last transfer in a write burst.
saxiacp_wvalid	O	Write valid. This signal indicates that valid write data and strobes are available. 1 = write data and strobes available 0 = write data and strobes not available
saxiacp_wready	O	Write ready. This signal indicates that the slave can accept the write data. 1 = slave ready 0 = slave not ready
saxiacp_bid	O	Response ID. The identification tag of the write response
saxiacp_bresp	O	Write response. This signal indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
saxiacp_bvalid	I	Write response valid. This signal indicates that a valid write response is available. 1 = write response available 0 = write response not available
saxiacp_bready	I	Response ready. This signal indicates that the master can accept the response information. 1 = master ready 0 = master not ready
saxiacp_arid	I	Read address ID. This signal is the identification tag for the read address group of signals.
saxiacp_araddr	I	Read address. The read address bus gives the initial address of a read burst transaction.
saxiacp_arlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
saxiacp_arsize	I	Burst size. This signal indicates the size of each transfer in the burst.
saxiacp_arburst	I	Burst type. The burst type and the size information determine how the address for each transfer within the burst is calculated.
saxiacp_arlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
saxiacp_arcache	I	Cache type. This signal provides additional information about the cacheable characteristics of the transfer.
saxiacp_arprot	I	Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
saxiacp_arvalid	O	Read address valid. This signal indicates, when High, that the read address and control information is valid and remains stable until the address acknowledge signal, ARREADY, is High
saxiacp_arready	O	Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready
saxiacp_rid	O	Read ID tag. This signal is the ID tag of the read data group of signals.
saxiacp_rdata	O	Read data. The read data bus can be 8, 16, 32, 64, 128, 256, 512, or 1,024 bits wide.
saxiacp_rresp	O	Read response. This signal indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
saxiacp_rlast	I	Read last. This signal indicates the last transfer in a read burst.
saxiacp_rvalid	O	Read valid. This signal indicates that the required read data is available and the read transfer can complete.
saxiacp_rready	O	Read ready. This signal indicates that the master can accept the read data and response information. 1= master ready 0 = master not ready
saxiacp_awqos	O	Wr addr channel QOS input.
saxiacp_arqos	O	Rd addr channel QOS input. Quality of service, sent for each read transaction.
pl_acpinact		ACP master is inactive and is not participating in coherency. When the master asserts this signal, ensure that there no outstanding transactions. Also, while this signal is asserted, the master must not send any new transactions. 0 : ACP Master is Active 1 : ACP Master is Inactive
pl_acpinact

Table B-50: S_AXI_ACP_FPD_ACLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxiacp_awuser	I	User signal. Optional user-defined signal in the write address channel
saxiacp_fpd_aclk	I	Input clock signal

Table B-51: S_AXI_HP0_FPD
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp2_aruser	I	User-defined AR channel signals
saxigp2_awuser	I	User-defined AW channel signals
saxigp2_awid	I	Write address ID. This signal is the identification tag for the write address group of signals.
saxigp2_awaddr	I	Write address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
saxigp2_awlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
saxigp2_awsize	I	Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
saxigp2_awburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
saxigp2_awlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
saxigp2_awcache	I	Cache type. This signal indicates the buffer able, cacheable, write-through, write-back, and allocate attributes of the transaction.
saxigp2_awprot	I	Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
saxigp2_awvalid	I	Write address valid. This signal indicates that valid write address and control information are available. 1 = address and control information available 0 = address and control information not available. The address and control information remain stable until the address acknowledge signal, AWREADY, goes High.
saxigp2_awready	O	Write address channel ready signal
saxigp2_wdata	I	Write data. The write data bus can be 32, 64, or 128 bits wide
saxigp2_wstrb	I	Write strobes. This signal indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
saxigp2_wlast	I	Write last. This signal indicates the last transfer in a write burst.
saxigp2_wvalid	I	Write valid. This signal indicates that valid write data and strobes are available. 1 = write data and strobes available 0 = write data and strobes not available
saxigp2_wready	O	Write ready. This signal indicates that the slave can accept the write data. 1 = slave ready 0 = slave not ready
saxigp2_bid	O	Response ID. The identification tag of the write response
saxigp2_bresp	O	Write response. This signal indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
saxigp2_bvalid	O	Write response valid. This signal indicates that a valid write response is available. 1 = write response available 0 = write response not available
saxigp2_bready	I	Response ready. This signal indicates that the master can accept the response information. 1 = master ready 0 = master not ready
saxigp2_arid	I	Read address ID. This signal is the identification tag for the read address group of signals.
saxigp2_araddr	I	Read address. The read address bus gives the initial address of a read burst transaction.
saxigp2_arlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
saxigp2_arsize	I	Burst size. This signal indicates the size of each transfer in the burst.
saxigp2_arburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
saxigp2_arlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
saxigp2_arcache	I	Cache type. This signal provides additional information about the cacheable characteristics of the transfer.
saxigp2_arprot	I	Protection type. This signal provides protection unit information for the transaction.
saxigp2_arvalid	I	Read address valid. This signal indicates, when High, that the read address and control information is valid and remains stable until the address acknowledge signal, ARREADY, is High.
saxigp2_arready	O	Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready
saxigp2_rid	O	Read ID tag. This signal is the ID tag of the read data group of signals.
saxigp2_rdata	O	Read data. The read data bus can be 8, 16, 32, 64, 128, 256, 512, or 1,024 bits wide.
saxigp2_rresp	O	Read response. This signal indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
saxigp2_rlast	O	Read last. This signal indicates the last transfer in a read burst.
saxigp2_rvalid	O	Read valid. This signal indicates that the required read data is available and the read transfer can complete.
saxigp2_rready	I	Read ready. This signal indicates that the master can accept the read data and response information. 1= master ready 0 = master not ready
saxigp2_awqos	O	Wr addr channel QOS input
saxigp2_arqos	O	Rd addr channel QOS input
saxigp2_rcount	O	Rd data channel fill level
saxigp2_wcount	O	Wr data channel fill level
saxigp2_racount	O	Rd addr channel fill level
saxigp2_wacount	O	Wr addr channel fill level

Table B-52: S_AXI_HP0_FPD_ACLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp2_aruser	I	User-defined AR channel signals
saxihp0_fpd_aclk	I	Input clock signal

Table B-53: S_AXI_HP0_FPD_RCLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp2_aruser	I	User-defined AR channel signals
saxihp0_fpd_rclk	I	Read clock signal

Table B-54: S_AXI_HP0_FPD_WCLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp2_aruser	I	User-defined AR channel signals0
saxihp0_fpd_wclk	I	Write clock signal

Table B-55: S_AXI_HP1_FPD
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp3_aruser	I	User-defined AR channel signals
saxigp3_awuser	I	User-defined AW channel signals
saxigp3_awid	I	Write address ID. This signal is the identification tag for the write address group of signals.
saxigp3_awaddr	I	Write address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
saxigp3_awlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
saxigp3_awsize	I	Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
saxigp3_awburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
saxigp3_awlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
saxigp3_awcache	I	Cache type. This signal indicates the buffer able, cacheable, write-through, write-back, and allocate attributes of the transaction.
saxigp3_awprot	I	Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
saxigp3_awvalid	I	Write address valid. This signal indicates that valid write address and control information are available. 1 = address and control information available 0 = address and control information not available The address and control information remain stable until the address acknowledge signal, AWREADY, goes High.
saxigp3_awready	O	Write address channel ready signal
saxigp3_wdata	I	Write data. The write data bus can be 32, 64, or 128 bits wide.
saxigp3_wstrb	I	Write strobes. This signal indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
saxigp3_wlast	I	Write last. This signal indicates the last transfer in a write burst.
saxigp3_wvalid	I	Write valid. This signal indicates that valid write data and strobes are available. 1 = write data and strobes available 0 = write data and strobes not available
saxigp3_wready	O	Write ready. This signal indicates that the slave can accept the write data. 1 = slave ready 0 = slave not ready
saxigp3_bid	O	Response ID. The identification tag of the write response
saxigp3_bresp	O	Write response. This signal indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
saxigp3_bvalid	O	Write response valid. This signal indicates that a valid write response is available. 1 = write response available 0 = write response not available
saxigp3_bready	I	Response ready. This signal indicates that the master can accept the response information. 1 = master ready 0 = master not ready
saxigp3_arid	I	Read address ID. This signal is the identification tag for the read address group of signals.
saxigp3_araddr	I	Read address. The read address bus gives the initial address of a read burst transaction.
saxigp3_arlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
saxigp3_arsize	I	Burst size. This signal indicates the size of each transfer in the burst
saxigp3_arburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
saxigp3_arlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
saxigp3_arcache	I	Cache type. This signal provides additional information about the cacheable characteristics of the transfer.
saxigp3_arprot	I	Protection type. This signal provides protection unit information for the transaction.
saxigp3_arvalid	I	Read address valid. This signal indicates, when High, that the read address and control information is valid and remains stable until the address acknowledge signal, ARREADY, is High.
saxigp3_arready	O	Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready
saxigp3_rid	O	Read ID tag. This signal is the ID tag of the read data group of signals.
saxigp3_rdata	O	Read data. The read data bus can be 8, 16, 32, 64, 128, 256, 512, or 1,024 bits wide.
saxigp3_rresp	O	Read response. This signal indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
saxigp3_rlast	O	Read last. This signal indicates the last transfer in a read burst.
saxigp3_rvalid	O	Read valid. This signal indicates that the required read data is available and the read transfer can complete.
saxigp3_rready	I	Read ready. This signal indicates that the master can accept the read data and response information. 1= master ready 0 = master not ready
saxigp3_awqos	O	Wr addr channel QOS input
saxigp3_arqos	O	Rd addr channel QOS input
saxigp3_rcount	O	Rd data channel fill level
saxigp3_wcount	O	Wr data channel fill level
saxigp3_racount	O	Rd addr channel fill level
saxigp3_wacount	O	Wr addr channel fill level

Table B-56: S_AXI_HP1_FPD_ACLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp3_aruser	I	User-defined AR channel signals
Saxihp1_fpd_aclk	I	Input clock signal

Table B-57: S_AXI_HP1_FPD_RCLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp3_aruser	I	User-defined AR channel signals
Saxihp1_fpd_rclk	I	Read clock signal

Table B-58: S_AXI_HP1_FPD_WCLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp3_aruser	I	User-defined AR channel signals
saxihp1_fpd_wclk	I	Write clock signal

Table B-59: S_AXI_HP2_FPD
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp4_aruser	I	User-defined AR channel signals
saxigp4_awuser	I	User-defined AW channel signals
saxigp4_awid	I	Write address ID. This signal is the identification tag for the write address group of signals.
saxigp4_awaddr	I	Write address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
saxigp4_awlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
saxigp4_awsize	I	Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
saxigp4_awburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
saxigp4_awlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
saxigp4_awcache	I	Cache type. This signal indicates the buffer able, cacheable, write-through, write-back, and allocate attributes of the transaction.
saxigp4_awprot	I	Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
saxigp4_awvalid	I	Write address valid. This signal indicates that valid write address and control information are available. 1 = address and control information available 0 = address and control information not available The address and control information remain stable until the address acknowledge signal, AWREADY, goes High.
saxigp4_awready	O	Write address channel ready signal
saxigp4_wdata	I	Write data. The write data bus can be 32, 64, or 128 bits wide.
saxigp4_wstrb	I	Write strobes. This signal indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
saxigp4_wlast	I	Write last. This signal indicates the last transfer in a write burst.
saxigp4_wvalid	I	Write valid. This signal indicates that valid write data and strobes are available. 1 = write data and strobes available 0 = write data and strobes not available
saxigp4_wready	O	Write ready. This signal indicates that the slave can accept the write data. 1 = slave ready 0 = slave not ready
saxigp4_bid	O	Response ID. The identification tag of the write response
saxigp4_bresp	O	Write response. This signal indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
saxigp4_bvalid	O	Write response valid. This signal indicates that a valid write response is available. 1 = write response available 0 = write response not available
saxigp4_bready	I	Response ready. This signal indicates that the master can accept the response information. 1 = master ready 0 = master not ready
saxigp4_arid	I	Read address ID. This signal is the identification tag for the read address group of signals.
saxigp4_araddr	I	Read address. The read address bus gives the initial address of a read burst transaction.
saxigp4_arlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
saxigp4_arsize	I	Burst size. This signal indicates the size of each transfer in the burst.
saxigp4_arburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
saxigp4_arlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
saxigp4_arcache	I	Cache type. This signal provides additional information about the cacheable characteristics of the transfer.
saxigp4_arprot	I	Protection type. This signal provides protection unit information for the transaction.
saxigp4_arvalid	I	Read address valid. This signal indicates, when High, that the read address and control information is valid and remains stable until the address acknowledge signal, ARREADY, is High.
saxigp4_arready	O	Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready
saxigp4_rid	O	Read ID tag. This signal is the ID tag of the read data group of signals.
saxigp4_rdata	O	Read data. The read data bus can be 8, 16, 32, 64, 128, 256, 512, or 1,024 bits wide.
saxigp4_rresp	O	Read response. This signal indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
saxigp4_rlast	O	Read last. This signal indicates the last transfer in a read burst.
saxigp4_rvalid	O	Read valid. This signal indicates that the required read data is available and the read transfer can complete.
saxigp4_rready	I	Read ready. This signal indicates that the master can accept the read data and response information. 1= master ready 0 = master not ready
saxigp4_awqos	O	Wr addr channel QOS input
saxigp4_arqos	O	Rd addr channel QOS input
saxigp4_rcount	O	Rd data channel fill level
saxigp4_wcount	O	Wr data channel fill level
saxigp4_racount	O	Rd addr channel fill level
saxigp4_wacount	O	Wr addr channel fill level

Table B-60: S_AXI_HP2_FPD_ACLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp4_aruser	I	User-defined AR channel signals
Saxihp2_fpd_aclk	I	Input clock signal

Table B-61: S_AXI_HP2_FPD_RCLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp4_aruser	I	User-defined AR channel signals
Saxihp2_fpd_rclk	I	Read clock signal

Table B-62: S_AXI_HP2_FPD_WCLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp4_aruser	I	User-defined AR channel signals
Saxihp2_fpd_wclk	I	Write clock signal

Table B-63: S_AXI_HP3_FPD
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp5_aruser	I	User-defined AR channel signals
saxigp5_awuser	I	User-defined AW channel signals
saxigp5_awid	I	Write address ID. This signal is the identification tag for the write address group of signals.
saxigp5_awaddr	I	Write address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
saxigp5_awlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
saxigp5_awsize	I	Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
saxigp5_awburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
saxigp5_awlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
saxigp5_awcache	I	Cache type. This signal indicates the buffer able, cacheable, write-through, write-back, and allocate attributes of the transaction.
saxigp5_awprot	I	Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
saxigp5_awvalid	I	Write address valid. This signal indicates that valid write address and control information are available. 1 = address and control information available 0 = address and control information not available The address and control information remain stable until the address acknowledge signal, AWREADY, goes High.
saxigp5_awready	O	Write address channel ready signal
saxigp5_wdata	I	Write data. The write data bus can be 32, 64, or 128 bits wide.
saxigp5_wstrb	I	Write strobes. This signal indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
saxigp5_wlast	I	Write last. This signal indicates the last transfer in a write burst.
saxigp5_wvalid	I	Write valid. This signal indicates that valid write data and strobes are available. 1 = write data and strobes available 0 = write data and strobes not available
saxigp5_wready	O	Write ready. This signal indicates that the slave can accept the write data. 1 = slave ready 0 = slave not ready
saxigp5_bid	O	Response ID. The identification tag of the write response
saxigp5_bresp	O	Write response. This signal indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
saxigp5_bvalid	O	Write response valid. This signal indicates that a valid write response is available. 1 = write response available 0 = write response not available
saxigp5_bready	I	Response ready. This signal indicates that the master can accept the response information. 1 = master ready 0 = master not ready
saxigp5_arid	I	Read address ID. This signal is the identification tag for the read address group of signals.
saxigp5_araddr	I	Read address. The read address bus gives the initial address of a read burst transaction.
saxigp5_arlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
saxigp5_arsize	I	Burst size. This signal indicates the size of each transfer in the burst.
saxigp5_arburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
saxigp5_arlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
saxigp5_arcache	I	Cache type. This signal provides additional information about the cacheable characteristics of the transfer.
saxigp5_arprot	I	Protection type. This signal provides protection unit information for the transaction.
saxigp5_arvalid	I	Read address valid. This signal indicates, when High, that the read address and control information is valid and remains stable until the address acknowledge signal, ARREADY, is High.
saxigp5_arready	O	Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready
saxigp5_rid	O	Read ID tag. This signal is the ID tag of the read data group of signals.
saxigp5_rdata	O	Read data. The read data bus can be 8, 16, 32, 64, 128, 256, 512, or 1,024 bits wide.
saxigp5_rresp	O	Read response. This signal indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
saxigp5_rlast	O	Read last. This signal indicates the last transfer in a read burst.
saxigp5_rvalid	O	Read valid. This signal indicates that the required read data is available and the read transfer can complete.
saxigp5_rready	I	Read ready. This signal indicates that the master can accept the read data and response information. 1= master ready 0 = master not ready
saxigp5_awqos	O	Wr addr channel QOS input
saxigp5_arqos	O	Rd addr channel QOS input
saxigp5_rcount	O	Rd data channel fill level
saxigp5_wcount	O	Wr data channel fill level
saxigp5_racount	O	Rd addr channel fill level
saxigp5_wacount	O	Wr addr channel fill level

Table B-64: S_AXI_HP3_FPD_ACLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp5_aruser	I	User-defined AR channel signals
Saxihp3_fpd_aclk	I	Input clock signal

Table B-65: S_AXI_HP3_FPD_RCLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp5_aruser	I	User-defined AR channel signals
Saxihp3_fpd_rclk	I	Read clock signal

Table B-66: S_AXI_HP1_FPD_WCLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp5_aruser	I	User-defined AR channel signals
Saxihp3_fpd_wclk	I	Write clock signal

Table B-67: S_AXI_HPC0_FPD
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp0_aruser	I	User-defined AR channel signals
saxigp0_awuser	I	User-defined AW channel signals
saxigp0_awid	I	Write address ID. This signal is the identification tag for the write address group of signals.
saxigp0_awaddr	I	Write address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
saxigp0_awlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
saxigp0_awsize	I	Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
saxigp0_awburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
saxigp0_awlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
saxigp0_awcache	I	Cache type. This signal indicates the buffer able, cacheable, write-through, write-back, and allocate attributes of the transaction.
saxigp0_awprot	I	Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
saxigp0_awvalid	I	Write address valid. This signal indicates that valid write address and control information are available. 1 = address and control information available 0 = address and control information not available The address and control information remain stable until the address acknowledge signal, AWREADY, goes High.
saxigp0_awready	O	Write address channel ready signal
saxigp0_wdata	I	Write data. The write data bus can be 128 bits wide.
saxigp0_wstrb	I	Write strobes. This signal indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
saxigp0_wlast	I	Write last. This signal indicates the last transfer in a write burst.
saxigp0_wvalid	I	Write valid. This signal indicates that valid write data and strobes are available. 1 = write data and strobes available 0 = write data and strobes not available
saxigp0_wready	O	Write ready. This signal indicates that the slave can accept the write data. 1 = slave ready 0 = slave not ready
saxigp0_bid	O	Response ID. The identification tag of the write response
saxigp0_bresp	O	Write response. This signal indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
saxigp0_bvalid	O	Write response valid. This signal indicates that a valid write response is available. 1 = write response available 0 = write response not available
saxigp0_bready	I	Response ready. This signal indicates that the master can accept the response information. 1 = master ready 0 = master not ready
saxigp0_arid	I	Read address ID. This signal is the identification tag for the read address group of signals.
saxigp0_araddr	I	Read address. The read address bus gives the initial address of a read burst transaction.
saxigp0_arlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
saxigp0_arsize	I	Burst size. This signal indicates the size of each transfer in the burst.
saxigp0_arburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
saxigp0_arlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
saxigp0_arcache	I	Cache type. This signal provides additional information about the cacheable characteristics of the transfer.
saxigp0_arprot	I	Protection type. This signal provides protection unit information for the transaction.
saxigp0_arvalid	I	Read address valid. This signal indicates, when High, that the read address and control information is valid and remains stable until the address acknowledge signal, ARREADY, is High.
saxigp0_arready	O	Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready.
saxigp0_rid	O	Read ID tag. This signal is the ID tag of the read data group of signals.
saxigp0_rdata	O	Read data. The read data bus can be 8, 16, 32, 64, 128, 256, 512, or 1,024 bits wide.
saxigp0_rresp	O	Read response. This signal indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
saxigp0_rlast	O	Read last. This signal indicates the last transfer in a read burst.
saxigp0_rvalid	O	Read valid. This signal indicates that the required read data is available and the read transfer can complete.
saxigp0_rready	I	Read ready. This signal indicates that the master can accept the read data and response information. 1= master ready 0 = master not ready
saxigp0_awqos	O	Wr addr channel QOS input
saxigp0_arqos	O	Rd addr channel QOS input
saxigp0_rcount	O	Rd data channel fill level
saxigp0_wcount	O	Wr data channel fill level
saxigp0_racount	O	Rd addr channel fill level
saxigp0_wacount	O	Wr addr channel fill level

Table B-68: S_AXI_HPC0_FPD_ACLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp0_aruser	I	User-defined AR channel signals
saxihpc0_fpd_aclk	I	Input clock signal

Table B-69: S_AXI_HPC0_FPD_RCLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp0_aruser	I	User-defined AR channel signals
saxihpc0_fpd_rclk	I	Read clock signal

Table B-70: S_AXI_HPC0_FPD_WCLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp0_aruser	I	User-defined AR channel signals
saxihpc0_fpd_wclk	I	Write clock signal

Table B-71: S_AXI_HPC1_FPD
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
Saxigp1_aruser	I	User-defined AR channel signals
Saxigp1_awuser	I	User-defined AW channel signals
Saxigp1_awid	I	Write address ID. This signal is the identification tag for the write address group of signals.
Saxigp1_awaddr	I	Write address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
Saxigp1_awlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
Saxigp1_awsize	I	Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
Saxigp1_awburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
Saxigp1_awlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
Saxigp1_awcache	I	Cache type. This signal indicates the buffer able, cacheable, write-through, write-back, and allocate attributes of the transaction.
Saxigp1_awprot	I	Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
Saxigp1_awvalid	I	Write address valid. This signal indicates that valid write address and control information are available. 1 = address and control information available 0 = address and control information not available The address and control information remain stable until the address acknowledge signal, AWREADY, goes High.
Saxigp1_awready	O	Write address channel ready signal
Saxigp1_wdata	I	Write data. The write data bus can be 128 bits wide.
Saxigp1_wstrb	I	Write strobes. This signal indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
Saxigp1_wlast	I	Write last. This signal indicates the last transfer in a write burst.
Saxigp1_wvalid	I	Write valid. This signal indicates that valid write data and strobes are available. 1 = write data and strobes available 0 = write data and strobes not available
Saxigp1_wready	O	Write ready. This signal indicates that the slave can accept the write data. 1 = slave ready 0 = slave not ready
Saxigp1_bid	O	Response ID. The identification tag of the write response
Saxigp1_bresp	O	Write response. This signal indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
Saxigp1_bvalid	O	Write response valid. This signal indicates that a valid write response is available. 1 = write response available 0 = write response not available
Saxigp1_bready	I	Response ready. This signal indicates that the master can accept the response information. 1 = master ready 0 = master not ready
Saxigp1_arid	I	Read address ID. This signal is the identification tag for the read address group of signals.
Saxigp1_araddr	I	Read address. The read address bus gives the initial address of a read burst transaction.
Saxigp1_arlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
Saxigp1_arsize	I	Burst size. This signal indicates the size of each transfer in the burst.
Saxigp1_arburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
Saxigp1_arlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
Saxigp1_arcache	I	Cache type. This signal provides additional information about the cacheable characteristics of the transfer.
Saxigp1_arprot	I	Protection type. This signal provides protection unit information for the transaction.
Saxigp1_arvalid	I	Read address valid. This signal indicates, when High, that the read address and control information is valid and remains stable until the address acknowledge signal, ARREADY, is High.
Saxigp1_arready	O	Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready
Saxigp1_rid	O	Read ID tag. This signal is the ID tag of the read data group of signals.
Saxigp1_rdata	O	Read data. The read data bus can be 8, 16, 32, 64, 128, 256, 512, or 1,024 bits wide.
Saxigp1_rresp	O	Read response. This signal indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
Saxigp1_rlast	O	Read last. This signal indicates the last transfer in a read burst.
Saxigp1_rvalid	O	Read valid. This signal indicates that the required read data is available and the read transfer can complete.
Saxigp1_rready	I	Read ready. This signal indicates that the master can accept the read data and response information. 1= master ready 0 = master not ready
Saxigp1_awqos	O	Wr addr channel QOS input
Saxigp1_arqos	O	Rd addr channel QOS input
Saxigp1_rcount	O	Rd data channel fill level
Saxigp1_wcount	O	Wr data channel fill level
Saxigp1_racount	O	Rd addr channel fill level
Saxigp1_wacount	O	Wr addr channel fill level

Table B-72: S_AXI_HPC1_FPD_ACLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
Saxigp1_aruser	I	User-defined AR channel signals
Saxihpc1_fpd_aclk	I	Input clock signal

Table B-73: S_AXI_HPC1_FPD_RCLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
Saxigp1_aruser	I	User-defined AR channel signals
Saxihpc1_fpd_rclk	I	Read clock signal

Table B-74: S_AXI_HPC1_FPD_WCLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
Saxigp1_aruser	I	User-defined AR channel signals
Saxihpc1_fpd_wclk	I	Write clock signal

Table B-75: S_AXI_PL_LPD
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp6_aruser	I	User-defined AR channel signals
saxigp6_awuser	I	User-defined AW channel signals
saxigp6_awid	I	Write address ID. This signal is the identification tag for the write address group of signals.
saxigp6_awaddr	I	Write address. The write address bus gives the address of the first transfer in a write burst transaction. The associated control signals are used to determine the addresses of the remaining transfers in the burst.
saxigp6_awlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
saxigp6_awsize	I	Burst size. This signal indicates the size of each transfer in the burst. Byte lane strobes indicate exactly which byte lanes to update.
saxigp6_awburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
saxigp6_awlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
saxigp6_awcache	I	Cache type. This signal indicates the buffer able, cacheable, write-through, write-back, and allocate attributes of the transaction.
saxigp6_awprot	I	Protection type. This signal indicates the normal, privileged, or secure protection level of the transaction and whether the transaction is a data access or an instruction access.
saxigp6_awvalid	I	Write address valid. This signal indicates that valid write address and control information are available. 1 = address and control information available 0 = address and control information not available The address and control information remain stable until the address acknowledge signal, AWREADY, goes High.
saxigp6_awready	O	Write address channel ready signal
saxigp6_wdata	I	Write data. The write data bus can be 32, 64, or 128 bits wide.
saxigp6_wstrb	I	Write strobes. This signal indicates which byte lanes to update in memory. There is one write strobe for each eight bits of the write data bus.
saxigp6_wlast	I	Write last. This signal indicates the last transfer in a write burst.
saxigp6_wvalid	I	Write valid. This signal indicates that valid write data and strobes are available. 1 = write data and strobes available 0 = write data and strobes not available
saxigp6_wready	O	Write ready. This signal indicates that the slave can accept the write data. 1 = slave ready 0 = slave not ready
saxigp6_bid	O	Response ID. The identification tag of the write response
saxigp6_bresp	O	Write response. This signal indicates the status of the write transaction. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
saxigp6_bvalid	O	Write response valid. This signal indicates that a valid write response is available. 1 = write response available 0 = write response not available
saxigp6_bready	I	Response ready. This signal indicates that the master can accept the response information. 1 = master ready 0 = master not ready
saxigp6_arid	I	Read address ID. This signal is the identification tag for the read address group of signals.
saxigp6_araddr	I	Read address. The read address bus gives the initial address of a read burst transaction.
saxigp6_arlen	I	Burst length. The burst length gives the exact number of transfers in a burst. This information determines the number of data transfers associated with the address.
saxigp6_arsize	I	Burst size. This signal indicates the size of each transfer in the burst.
saxigp6_arburst	I	Burst type. The burst type, coupled with the size information, details how the address for each transfer within the burst is calculated.
saxigp6_arlock	I	Lock type. This signal provides additional information about the atomic characteristics of the transfer.
saxigp6_arcache	I	Cache type. This signal provides additional information about the cacheable characteristics of the transfer.
saxigp6_arprot	I	Protection type. This signal provides protection unit information for the transaction.
saxigp6_arvalid	I	Read address valid. This signal indicates, when High, that the read address and control information is valid and remains stable until the address acknowledge signal, ARREADY, is High.
saxigp6_arready	O	Read address ready. This signal indicates that the slave is ready to accept an address and associated control signals. 1 = slave ready 0 = slave not ready
saxigp6_rid	O	Read ID tag. This signal is the ID tag of the read data group of signals.
saxigp6_rdata	O	Read data. The read data bus can be 8, 16, 32, 64, 128, 256, 512, or 1,024 bits wide.
saxigp6_rresp	O	Read response. This signal indicates the status of the read transfer. The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.
saxigp6_rlast	O	Read last. This signal indicates the last transfer in a read burst.
saxigp6_rvalid	O	Read valid. This signal indicates that the required read data is available and the read transfer can complete.
saxigp6_rready	I	Read ready. This signal indicates that the master can accept the read data and response information. 1= master ready 0 = master not ready
saxigp6_awqos	O	Wr addr channel QOS input
saxigp6_arqos	O	Rd addr channel QOS input
saxigp6_rcount	O	Rd data channel fill level
saxigp6_wcount	O	Wr data channel fill level
saxigp6_racount	O	Rd addr channel fill level
saxigp6_wacount	O	Wr addr channel fill level

Table B-76: S_AXI_PL_LPD_ACLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp6_aruser	I	User-defined AR channel signals
saxipl_lpd_aclk	I	Input clock signal

Table B-77: S_AXI_PL_LPD_RCLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp6_aruser	I	User-defined AR channel signals
saxipl_lpd_rclk	I	Read clock signal

Table B-78: S_AXI_PL_LPD_WCLK
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
saxigp6_aruser	I	User-defined AR channel signals
saxipl_lpd_wclk	I	Write clock signal

Table B-79: USB Paramters
Zynq UltraScale + MPSoC PS I/O Name	I/O	Description
emio_u2dsport_vbus_ctrl_usb3_0	O	DC Voltage Bus (VBUS) control port signal for USB 2.0
emio_u3dsport_vbus_ctrl_usb3_0	O	DC Voltage Bus (VBUS) control port signal for USB 3.0