The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
06/16/2023 |
3.5 |
• Corrected core version. |
|
05/10/2022 |
3.4 |
• Added SD Configuration section in Chapter 4. • Added Dynamic DDR Configuration section in Chapter 4. • Added USB Parameters table in Appendix B. • Updated User Parameters table in Appendix C. |
|
06/10/2020 |
3.3 |
• Updated Interrupt numbers in Table 2-1. • Updated PS-PL section with detail description. • Updated CCI section with limitations. • Updated Known limitations section in Isolation Configurations. • Updated data widths supported by different GP ports in Appendix B. • Updated Notes section in User Parameters. |
|
01/06/2020 |
3.3 |
• Updated the figures as per the core version update in Chapter 4. • Updated IO Configuration, Clock Configuration, PS-PL Configuration, PCIe Configuration, and Simulation sections in Chapter 4. • Added DDR Traffic Class section in Chapter 4. |
|
12/05/2018 |
3.2 |
• Updated the PCIE address under PS-PL Configuration section in Chapter 4. • Updated the possible values for the PSU__USB__RESET__MODE, PSU__USB__RESET__POLARITY, PSU__USB0__RESET__ENABLE, PSU__USB0__RESET__IO,PSU__USB1__RESET__ENABLE and PSU__USB1__RESET__IO parameters in Appendix C. |
|
04/04/2018 |
3.2 |
• Updated the DDR Preset Selection and DDR Self-Refresh information under DDR Configuration section in Chapter 4. • Updated the figures as per the core version update in Chapter 4. • Updated Fractional Enablement feature details for ACPU and CCI Enablement section in Chapter 4. |
|
10/04/2017 |
3.1 |
• Updated signal range for signal Number 1 in Table 2-2. • Updated signals in Connectivity section in Chapter 2. • Added Fractional Clocking and Load DDR Presets sections to Chapter 4. • Updated Speed Bin option in DDR Memory Options in Chapter 4. • Updated Figures 4-1, 4-7, 4-9, and 4-10. • Added ten new options to the Other Options section in Chapter 4. • Updated Notice of Disclaimer and added Automotive Applications Disclaimer. • Added Preset Support section to Chapter 4. • Added new table for TSU signals in Appendix B. • Removed CONFIG. from several of the Parameters in Table C-1. • Removed SME parameters from Table C-1. |
|
04/05/2017 |
3.0 |
• Updated all the PCW screens as per the new look and feel changes in current Vivado IDE. • Updated Isolation settings configuration information in Chapter 4. • Updated clocking details of Output Clocks section in Chapter 4. • LPD_DMA (ADMA) and FPD_DMA(GDMA) signal names have been standardized across the guide. |
|
11/30/2016
|
2.0 |
• Updated Figure 4-7 and Figure 5-1. • Removed ECC Scrub from page 35. • Added I/O Configuration table to Appendix D, Port Descriptions. • Changed many port names in Appendix B, Port Descriptions. See Appendix A, Migrating and Updating for details. |
|
10/05/2016 |
2.0 |
• Added Updated all screen displays in Chapter 4. • Updated the GT Lane clocking description in Chapter 4. • Updated most of the DDR Configuration section in Chapter 4. • Added the PCIe Configuration and Isolation Configurations in PCW sections in Chapter 4. • Replaced User Parameters table in Appendix C. |
|
06/08/2016 |
1.2 |
• Updated Figures 4-2 through 4-7. • Changed all _t_n signals to _t and removed the word “INVERTED” from the descriptions. • Modified PSU_CAN0_PERIPHERAL_ENABLE and PSU_CAN1_PERIPHERAL_ENABLE parameter default to be 0. • Removed PSU_DPAUX_PERIPHERAL_ENABLE parameter. • Updated the possible values for the PSU_DPAUX_PERIPHERAL_IO, PSU_SD1_SPEED_MODE. and PSU_CRF_APB_TOPSW_MAIN_CTRL_FREQMHZ parameters. • Added the PSU__DISPLAYPORT__PERIPHERAL__ENABLE and PSU__DP__LANE_SEL parameters. • Modified “Gpio” to be “GPIO” • Updated many of the rows that were missing information in Table C-1. |
|
04/06/2016 |
1.1 |
• Added High Speed SerDes configuration feature. • Renamed Unsupported Features” section as “Unsupported Features and Known Limitations.” Removed all of the bulleted items. Added cross reference to the master answer record. • Removed ACP Transaction Checker section. • Removed NOR flash. • Updated AXI4 I/O Compliant Interfaces section. • Added data to Table 2-2, Device Utilization – Zynq UltraScale+ MPSoC. • Removed MicroBlaze information from the General Design Guidelines section. • Added or updated all screen displays in Chapter 4. • Replaced Drive 0 and Drive 1 fields with Drive Strength field. • Replaced Pull Enable and Pullup fields with Pull Type field • Added information about MIO and EMIO, Number of MIOs and their organization in the banks • Added brief details about SerDes configuration supported in PCW. • Added information about MIO Voltage standard; specified that the default voltage for the banks will be LVCMOM33 • Replaced Input Frequency field with Requested Freq (MHz) . • Replaced Actual Frequency field with Actual Frequency (MHz). • Replaced Range with Range (MHz) . • Added details about Cross Domain PLL, GT lane clocking, and Auto Vs Manual features. |
|
11/18/2015 |
1.0 |
Initial version for public access. |