°
AXI HP and sub options – There are two (AXI HPC0 FPD, AXI HPC1 FPD) high performance AXI I/O coherent master interfaces in full-power domain; four (AXI HP0 FPD, AXI HP1 FPD, AXI HP2 FPD, AXI HP3 FPD) high performance slave AXI interfaces in full-power domain; one (AXI LPD) AXI interface in low-power domain.
Each interface supports 32, 64, and 128 data widths.
° S AXI ACP – There is one Accelerator Coherency Port that can be connected to a DMA engine or a non-cached coherent master.
° S AXI ACE – There is one AXI Coherency Extension slave.
|
Interface Name |
Abbreviation |
FIFO Interface |
Master |
Usage Description |
|---|---|---|---|---|
|
S_AXI_HP{0:3}_FPD |
HP{0:3} |
AFI_{2:5} |
PL |
Non-coherent paths from PL to FPD main switch and DDR |
|
S_AXI_LPD |
PL_LPD |
AFI_6 |
PL |
Non-coherent path from PL to IOP in LPD |
|
S_AXI_ACE_FPD |
ACE |
None |
PL |
Two-way coherent path between memory in PL and CCI |
|
S_AXI_ACP_FPD |
ACP |
None |
PL |
Legacy coherency. I/O coherent with L2 cache allocation. |
|
S_AXI_HPC{0, 1}_FPD |
HPC{0,1} |
AFI_{0:1} |
PL |
I/O coherent with CCI. No L2 cache allocation |
|
M_AXI_HPM{0, 1}_FPD |
HPM{0,1} |
None |
PS |
FPD masters to PL slaves |
|
M_AXI_HPM0_LPD |
LPD_PL |
None |
PS |
LPD masters to PL slaves |