User Parameters - 3.5 English

Zynq UltraScale+ MPSoC Processing System Product Guide
Document ID
PG201
Release Date
2023-06-16
Version
3.5 English
Table C-1: User Parameters

Parameter Description

Parameters

Range

Default
Values

PSS Input frequency

PSU__PSS_REF_CLK__FREQMHZ

33.333

PSU__PSS_ALT_REF_CLK__FREQMHZ

33.333

Video Ref Clk Frequency

PSU__VIDEO_REF_CLK__FREQMHZ

33.333

PSU__AUX_REF_CLK__FREQMHZ

33.333

PSU__GT_REF_CLK__FREQMHZ

33.333

PSU__VIDEO_REF_CLK__ENABLE

0,1

0

PSU__VIDEO_REF_CLK__IO

<Select>,MIO 27,MIO 50

<Select>

PSU__PSS_ALT_REF_CLK__ENABLE

0,1

0

PSU__PSS_ALT_REF_CLK__IO

<Select>,MIO 28,MIO 51

<Select>

CAN Peripheral Related parameters

PSU__CAN0__PERIPHERAL__ENABLE

0,1

0

PSU__CAN0__PERIPHERAL__IO

<Select>,EMIO,MIO 2 .. 3,
MIO 6 .. 7,MIO 10 .. 11,
MIO 14 .. 15,MIO 18 .. 19,
MIO 22 .. 23,MIO 26 .. 27,
MIO 30 .. 31,MIO 34 .. 35,
MIO 38 .. 39,MIO 42 .. 43,
MIO 46 .. 47,MIO 50 .. 51,
MIO 54 .. 55,MIO 58 .. 59,
MIO 62 .. 63,MIO 66 .. 67,
MIO 70 .. 71,MIO 74 .. 75

<Select>

PSU__CAN0__GRP_CLK__ENABLE

0,1

0

CAN Peripheral Related parameters

(continued)

PSU__CAN0__GRP_CLK__IO

<Select>,MIO 0,MIO 1,MIO 2,
MIO 3,MIO 4,MIO 5,MIO 6,
MIO 7,MIO 8,MIO 9,MIO 10,
MIO 11,MIO 12,MIO 13,
MIO 14,MIO 15,MIO 16,
MIO 17,MIO 18,MIO 19,
MIO 20,MIO 21,MIO 22,
MIO 23,MIO 24,MIO 25,
MIO 26,MIO 27,MIO 28,
MIO 29,MIO 30,MIO 31,
MIO 32,MIO 33,MIO 34,
MIO 35,MIO 36,MIO 37,
MIO 38,MIO 39,MIO 40,
MIO 41,MIO 42,MIO 43,
MIO 44,MIO 45,MIO 46,
MIO 47,MIO 48,MIO 49,
MIO 50,MIO 51,MIO 52,
MIO 53,MIO 54,MIO 55,
MIO 56,MIO 57,MIO 58,
MIO 59,MIO 60,MIO 61,
MIO 62,MIO 63,MIO 64,
MIO 65,MIO 66,MIO 67,
MIO 68,MIO 69,MIO 70,
MIO 71,MIO 72,MIO 73,
MIO 74,MIO 75,MIO 76,MIO 77

<Select>

PSU__CAN1__PERIPHERAL__ENABLE

0,1

0

PSU__CAN1__PERIPHERAL__IO

<Select>,EMIO,MIO 0 .. 1,
MIO 4 .. 5,MIO 8 .. 9,
MIO 12 .. 13,MIO 16 .. 17,
MIO 20 .. 21,MIO 24 .. 25,
MIO 28 .. 29,MIO 32 .. 33,
MIO 36 .. 37,MIO 40 .. 41,
MIO 44 .. 45,MIO 48 .. 49,
MIO 52 .. 53,MIO 56 .. 57,
MIO 60 .. 61,MIO 64 .. 65,
MIO 68 .. 69,MIO 72 .. 73,
MIO 76 .. 77

<Select>

PSU__CAN1__GRP_CLK__ENABLE

0,1

0

CAN Peripheral Related parameters

(continued)

PSU__CAN1__GRP_CLK__IO

<Select>,MIO 0,MIO 1,MIO 2,
MIO 3,MIO 4,MIO 5,MIO 6,
MIO 7,MIO 8,MIO 9,MIO 10,
MIO 11,MIO 12,MIO 13,
MIO 14,MIO 15,MIO 16,
MIO 17,MIO 18,MIO 19,
MIO 20,MIO 21,MIO 22,
MIO 23,MIO 24,MIO 25,
MIO 26,MIO 27,MIO 28,
MIO 29,MIO 30,MIO 31,
MIO 32,MIO 33,MIO 34,
MIO 35,MIO 36,MIO 37,
MIO 38,MIO 39,MIO 40,
MIO 41,MIO 42,MIO 43,
MIO 44,MIO 45,MIO 46,
MIO 47,MIO 48,MIO 49,
MIO 50,MIO 51,MIO 52,
MIO 53,MIO 54,MIO 55,
MIO 56,MIO 57,MIO 58,
MIO 59,MIO 60,MIO 61,
MIO 62,MIO 63,MIO 64,
MIO 65,MIO 66,MIO 67,
MIO 68,MIO 69,MIO 70,
MIO 71,MIO 72,MIO 73,
MIO 74,MIO 75,MIO 76,MIO 77

<Select>

PSU__CAN0_LOOP_CAN1__ENABLE

0,1

0

PSU__DPAUX__PERIPHERAL__ENABLE

0,1

0

PSU__DPAUX__PERIPHERAL__IO

<Select>,MIO 27 .. 30,
MIO 34 .. 37,EMIO

<Select>

ENET Related Parameters

PSU__ENET0__GRP_MDIO__ENABLE

0,1

0

CONFIG.PSU__ENET0__FIFO__ENABLE

0,1

0

CONFIG.PSU__ENET0__PTP__ENABLE

0,1

0

PSU__ENET0__GRP_MDIO__IO

<Select>,EMIO,MIO 76 .. 77

<Select>

PSU__GEM__TSU__ENABLE

0,1

0

PSU__GEM__TSU__IO

<Select>,EMIO,MIO 26,
MIO 50,MIO 51

<Select>

PSU__ENET0__PERIPHERAL__ENABLE

0,1

0

PSU__ENET0__PERIPHERAL__IO

<Select>,EMIO,GT Lane0,
MIO 26 .. 37

<Select>

PSU__ENET1__PERIPHERAL__ENABLE

0,1

0

PSU__ENET1__PERIPHERAL__IO

<Select>,EMIO,MIO 38 .. 49,
GT Lane1

<Select>

PSU__ENET1__GRP_MDIO__ENABLE

0,1

0

PSU__ENET1__FIFO__ENABLE

0,1

0

PSU__ENET1__PTP__ENABLE

0,1

0

PSU__FPGA_PL0_ENABLE

0,1

1

PSU__FPGA_PL1_ENABLE

0,1

0

PSU__FPGA_PL2_ENABLE

0,1

0

PSU__FPGA_PL3_ENABLE

0,1

0

ENET Related Parameters

(Continued)

PSU__ENET1__GRP_MDIO__IO

<Select>,EMIO,MIO 50 .. 51,
MIO 76 .. 77

<Select>

PSU__ENET2__PERIPHERAL__ENABLE

0,1

0

PSU__ENET2__PERIPHERAL__IO

<Select>,EMIO,GT Lane2,
MIO 52 .. 63

<Select>

PSU__ENET2__GRP_MDIO__ENABLE

0,1

0

PSU__ENET2__FIFO__ENABLE

0,1

0

PSU__ENET2__PTP__ENABLE

0,1

0

PSU__ENET2__GRP_MDIO__IO

<Select>,EMIO,MIO 76 .. 77

<Select>

PSU__ENET3__PERIPHERAL__ENABLE

0,1

0

PSU__ENET3__PERIPHERAL__IO

<Select>,EMIO,GT Lane3,
MIO 64 .. 75

<Select>

PSU__ENET3__GRP_MDIO__ENABLE

0,1

0

PSU__ENET3__FIFO__ENABLE

0,1

0

PSU__ENET3__PTP__ENABLE

0,1

0

PSU__ENET3__GRP_MDIO__IO

<Select>,EMIO,MIO 76 .. 77

<Select>

GPIO Related Parameters

PSU__GPIO_EMIO__PERIPHERAL__
ENABLE

0,1

0

PSU__GPIO_EMIO__PERIPHERAL__IO

<Select>

<Select>

PSU__GPIO0_MIO__PERIPHERAL__
ENABLE

0,1

0

PSU__GPIO0_MIO__IO

<Select>,MIO 0 .. 25

<Select>

PSU__GPIO1_MIO__PERIPHERAL__
ENABLE

0,1

0

PSU__GPIO1_MIO__IO

<Select>,MIO 26 .. 51

<Select>

PSU__GPIO2_MIO__PERIPHERAL__
ENABLE

0,1

0

PSU__GPIO2_MIO__IO

<Select>,MIO 52 .. 77

<Select>

I2C Related Parameters

PSU__I2C0__PERIPHERAL__ENABLE

0,1

0

PSU__I2C0__PERIPHERAL__IO

<Select>,EMIO,MIO 2 .. 3,
MIO 6 .. 7,MIO 10 .. 11,
MIO 14 .. 15,MIO 18 .. 19,
MIO 22 .. 23,MIO 26 .. 27,
MIO 30 .. 31,MIO 34 .. 35,
MIO 38 .. 39,MIO 42 .. 43,
MIO 46 .. 47,MIO 50 .. 51,
MIO 54 .. 55,MIO 58 .. 59,
MIO 62 .. 63,MIO 66 .. 67,
MIO 70 .. 71,MIO 74 .. 75

<Select>

PSU__I2C0__GRP_INT__ENABLE

0,1

0

PSU__I2C0__GRP_INT__IO

<Select>

<Select>

PSU__I2C1__PERIPHERAL__ENABLE

0,1

0

I2C Related Parameters

(continued)

PSU__I2C1__PERIPHERAL__IO

<Select>,EMIO,MIO 0 .. 1,
MIO 4 .. 5,MIO 8 .. 9,
MIO 12 .. 13,MIO 16 .. 17,
MIO 20 .. 21,MIO 24 .. 25,
MIO 28 .. 29,
MIO 32 .. 33,MIO 36 .. 37,
MIO 40 .. 41,MIO 44 .. 45,
MIO 48 .. 49,MIO 52 .. 53,
MIO 56 .. 57,MIO 60 .. 61,
MIO 64 .. 65,MIO 68 .. 69,
MIO 72 .. 73,MIO 76 .. 77

<Select>

PSU__I2C1__GRP_INT__ENABLE

0,1

0

PSU__I2C1__GRP_INT__IO

<Select>

<Select>

PSU__I2C0_LOOP_I2C1__ENABLE

0,1

0

PSU__TESTSCAN__PERIPHERAL__
ENABLE

0,1

0

PCIE Peripheral Enable

PSU__PCIE__PERIPHERAL__ENABLE

0,1

0

PSU__PCIE__PERIPHERAL__ENDPOINT_
ENABLE

0,1

1

PSU__PCIE__PERIPHERAL__ROOTPORT_
ENABLE

0,1

0

PSU__PCIE__PERIPHERAL__ENDPOINT_
IO

<Select>,MIO 29,MIO 30,
MIO 31,MIO 33,MIO 34,
MIO 35,MIO 36,MIO 37

<Select>

PSU__PCIE__PERIPHERAL__ROOTPORT_
IO

<Select>,MIO 0,MIO 1,MIO 2,
MIO 3,MIO 4,MIO 5,MIO 6,
MIO 7,MIO 8,MIO 9,MIO 10,
MIO 11,MIO 12,MIO 13,
MIO 14,MIO 15,MIO 16,
MIO 17,MIO 18,MIO 19,
MIO 20,MIO 21,MIO 22,
MIO 23,MIO 24,MIO 25,
MIO 26,MIO 27,MIO 28,
MIO 29,MIO 30,MIO 31,
MIO 32,MIO 33,MIO 34,
MIO 35,MIO 36,MIO 37,
MIO 38,MIO 39,MIO 40,MIO 41,
MIO 42,MIO 43,MIO 44,
MIO 45,MIO 46,MIO 47,
MIO 48,MIO 49,MIO 50,
MIO 51,MIO 52,MIO 53,
MIO 54,MIO 55,MIO 56,MIO 57,
MIO 58,MIO 59,MIO 60,
MIO 61,MIO 62,MIO 63,
MIO 64,MIO 65,MIO 66,
MIO 67,MIO 68,MIO 69,
MIO 70,MIO 71,MIO 72,
MIO 73,MIO 74,MIO 75,
MIO 76,MIO 77

<Select>

PCIE Lane Selections

PSU__PCIE__LANE0__ENABLE

0,1

0

PSU__PCIE__LANE0__IO

<Select>,GT Lane0

<Select>

PSU__PCIE__LANE1__ENABLE

0,1

0

PSU__PCIE__LANE1__IO

<Select>,GT Lane1

<Select>

PSU__PCIE__LANE2__ENABLE

0,1

0

PSU__PCIE__LANE2__IO

<Select>,GT Lane2

<Select>

PSU__PCIE__LANE3__ENABLE

0,1

0

PSU__PCIE__LANE3__IO

<Select>,GT Lane3

<Select>

PSU__GT__LINK_SPEED

<Select>,RBR,HBR,HBR2

<Select>

PSU__GT__VLT_SWNG_LVL_4

NA

PSU__GT__PRE_EMPH_LVL_4

NA

USB Related Parameters

PSU__USB0__REF_CLK_SEL

<Select>,Ref Clk0,Ref Clk1,
Ref Clk2,Ref Clk3

<Select>

PSU__USB0__REF_CLK_FREQ

<Select>,26,52,100

<Select>

PSU__USB1__REF_CLK_SEL

<Select>,Ref Clk0,Ref Clk1,
Ref Clk2,Ref Clk3

<Select>

PSU__USB1__REF_CLK_FREQ

<Select>,26,52,100

<Select>

GEM Ref CLK

PSU__GEM0__REF_CLK_SEL

<Select>,Ref Clk0,Ref Clk1,
Ref Clk2,Ref Clk3

<Select>

PSU__GEM0__REF_CLK_FREQ

<Select>,125

<Select>

PSU__GEM1__REF_CLK_SEL

<Select>,Ref Clk0,Ref Clk1,
Ref Clk2,Ref Clk3

<Select>

PSU__GEM1__REF_CLK_FREQ

<Select>,125

<Select>

PSU__GEM2__REF_CLK_SEL

<Select>,Ref Clk0,Ref Clk1,
Ref Clk2,Ref Clk3

<Select>

PSU__GEM2__REF_CLK_FREQ

<Select>,125

<Select>

PSU__GEM3__REF_CLK_SEL

<Select>,Ref Clk0,Ref Clk1,
Ref Clk2,Ref Clk3

<Select>

PSU__GEM3__REF_CLK_FREQ

<Select>,125

<Select>

DP Ref Clk

PSU__DP__REF_CLK_SEL

<Select>,Ref Clk0,Ref Clk1,
Ref Clk2,Ref Clk3

<Select>

PSU__DP__REF_CLK_FREQ

<Select>,27,108,135

<Select>

SATA Ref Clk

PSU__SATA__REF_CLK_SEL

<Select>,Ref Clk0,Ref Clk1,
Ref Clk2,Ref Clk3

<Select>

PSU__SATA__REF_CLK_FREQ

<Select>,150,125

<Select>

PCIE Ref Clk

PSU__PCIE__REF_CLK_SEL

<Select>,Ref Clk0,Ref Clk1,
Ref Clk2,Ref Clk3

<Select>

PSU__PCIE__REF_CLK_FREQ

<Select>,100

<Select>

DP Lane Selection

PSU__DP__LANE_SEL

<Select>,Dual Higher,Dual Lower,Single Higher,Single Lower

<Select>

PCIE Related Parameters

PSU__PCIE__DEVICE_PORT_TYPE

<Select>,Root Port,
Endpoint Device

<Select>

PSU__PCIE__MAXIMUM_LINK_WIDTH

<Select>,x1,x2,x4

<Select>

PSU__PCIE__LINK_SPEED

<Select>,2.5 Gb/s,5.0 Gb/s

<Select>

PSU__PCIE__INTERFACE_WIDTH

<Select>,64bit

<Select>

PSU__PCIE__BAR0_ENABLE

0,1

0

PSU__PCIE__BAR0_TYPE

<Select>,Memory,IO

<Select>

PSU__PCIE__BAR0_SCALE

<Select>,Bytes,Kilobytes,
Megabytes,Gigabytes,Terabytes
,Petabytes,Exabytes

<Select>

PSU__PCIE__BAR0_64BIT

0,1

0

PSU__PCIE__BAR0_SIZE

<Select>,1,2,4,8,16,32,64,128,
256,512

<Select>

PSU__PCIE__BAR0_VAL

NA

PSU__PCIE__BAR0_PREFETCHABLE

0,1

0

PSU__PCIE__BAR1_ENABLE

0,1

0

PSU__PCIE__BAR1_TYPE

<Select>,Memory,IO

<Select>

PSU__PCIE__BAR1_SCALE

<Select>,Bytes,Kilobytes,
Megabytes,Gigabytes,Terabytes,
Petabytes,Exabytes

<Select>

PSU__PCIE__BAR1_64BIT

0,1

0

PSU__PCIE__BAR1_SIZE

<Select>,1,2,4,8,16,32,64,128,
256,512

<Select>

PSU__PCIE__BAR1_VAL

NA

PSU__PCIE__BAR1_PREFETCHABLE

0,1

0

PSU__PCIE__BAR2_ENABLE

0,1

0

PSU__PCIE__BAR2_TYPE

<Select>,Memory

<Select>

PSU__PCIE__BAR2_SCALE

<Select>,Bytes,Kilobytes,
Megabytes,Gigabytes,Terabytes,
Petabytes,Exabytes

<Select>

PSU__PCIE__BAR2_64BIT

0,1

0

PSU__PCIE__BAR2_SIZE

<Select>,1,2,4,8,16,32,64,128,
256,512

<Select>

PSU__PCIE__BAR2_VAL

NA

PSU__PCIE__BAR2_PREFETCHABLE

0,1

0

PSU__PCIE__BAR3_ENABLE

0,1

0

PCIE Related Parameters

(continued)

PSU__PCIE__BAR3_TYPE

<Select>,Memory

<Select>

PSU__PCIE__BAR3_SCALE

<Select>,Bytes,Kilobytes,
Megabytes,Gigabytes,Terabytes,
Petabytes,Exabytes

<Select>

PSU__PCIE__BAR3_64BIT

0,1

0

PSU__PCIE__BAR3_SIZE

<Select>,1,2,4,8,16,32,64,128,
256,512

<Select>

PSU__PCIE__BAR3_VAL

NA

PSU__PCIE__BAR3_PREFETCHABLE

0,1

0

PSU__PCIE__BAR4_ENABLE

0,1

0

PSU__PCIE__BAR4_TYPE

<Select>,Memory

<Select>

PSU__PCIE__BAR4_SCALE

<Select>,Bytes,Kilobytes,
Megabytes,Gigabytes,Terabytes,
Petabytes,Exabytes

<Select>

PSU__PCIE__BAR4_64BIT

0,1

0

PSU__PCIE__BAR4_SIZE

<Select>,1,2,4,8,16,32,64,128,
256,512

<Select>

PSU__PCIE__BAR4_VAL

NA

PSU__PCIE__BAR4_PREFETCHABLE

0,1

0

PSU__PCIE__BAR5_ENABLE

0,1

0

PSU__PCIE__BAR5_TYPE

<Select>,Memory

<Select>

PSU__PCIE__BAR5_SCALE

<Select>,Bytes,Kilobytes,
Megabytes,Gigabytes

<Select>

PSU__PCIE__BAR5_64BIT

0,1

0

PSU__PCIE__BAR5_SIZE

<Select>,1,2,4,8,16,32,64,128,
256,512

<Select>

PSU__PCIE__BAR5_VAL

NA

PSU__PCIE__BAR5_PREFETCHABLE

0,1

0

PSU__PCIE__EROM_ENABLE

0,1

0

PCIE Related Parameters

(continued)

PSU__PCIE__EROM_SCALE

<Select>,Kilobytes,Megabytes,
Gigabytes

<Select>

PSU__PCIE__EROM_SIZE

<Select>,2,4,8,16,32,64,128,256,
512

<Select>

PSU__PCIE__EROM_VAL

NA

PSU__PCIE__CAP_SLOT_IMPLEMENTED

<Select>

<Select>

PSU__PCIE__MAX_PAYLOAD_SIZE

<Select>,128 bytes,256 bytes

<Select>

PSU__PCIE__LEGACY_INTERRUPT

<Select>

<Select>

PSU__PCIE__VENDOR_ID

NA

PSU__PCIE__DEVICE_ID

NA

PSU__PCIE__REVISION_ID

NA

PSU__PCIE__SUBSYSTEM_VENDOR_ID

NA

PSU__PCIE__SUBSYSTEM_ID

NA

PSU__PCIE__BASE_CLASS_MENU

See Note (1)

for values


<Select>

PSU__PCIE__USE_CLASS_CODE_LOOKUP_ASSISTANT

<Select>,0,1

<Select>

PSU__PCIE__SUB_CLASS_INTERFACE_
MENU

<Select>,
Computer telephony device,
Audio device,Video device,
Other multimedia device

<Select>

PSU__PCIE__CLASS_CODE_BASE

NA

PSU__PCIE__CLASS_CODE_SUB

NA

PSU__PCIE__CLASS_CODE_INTERFACE

NA

PSU__PCIE__CLASS_CODE_VALUE

NA

PSU__PCIE__AER_CAPABILITY

0,1

0

PSU__PCIE__CORRECTABLE_INT_ERR

0,1

0

PSU__PCIE__HEADER_LOG_OVERFLOW

0,1

0

PSU__PCIE__RECEIVER_ERR

0,1

0

PSU__PCIE__SURPRISE_DOWN

0,1

0

PCIE Related

Parameters

(continued)

PSU__PCIE__FLOW_CONTROL_ERR

0,1

0

PSU__PCIE__COMPLTION_TIMEOUT

0,1

0

PSU__PCIE__COMPLETER_ABORT

0,1

0

PSU__PCIE__RECEIVER_OVERFLOW

0,1

0

PSU__PCIE__ECRC_ERR

0,1

0

PSU__PCIE__ACS_VIOLAION

NA

NA

PSU__PCIE__UNCORRECTABL_INT_ERR

0,1

0

PSU__PCIE__MC_BLOCKED_TLP

0,1

0

PSU__PCIE__ATOMICOP_EGRESS_BLOCKED

0,1

0

PSU__PCIE__TLP_PREFIX_BLOCKED

0,1

0

PSU__PCIE__FLOW_CONTROL_
PROTOCOL_ERR

0,1

0

PSU__PCIE__ACS_VIOLATION

0,1

0

PSU__PCIE__MULTIHEADER

0,1

0

PSU__PCIE__ECRC_CHECK

0,1

0

PSU__PCIE__ECRC_GEN

0,1

0

PSU__PCIE__PERM_ROOT_ERR_
UPDATE

0,1

0

PSU__PCIE__CRS_SW_VISIBILITY

0,1

0

PSU__PCIE__INTX_GENERATION

0,1

0

PSU__PCIE__INTX_PIN

<Select>,INTA

<Select>

PSU__PCIE__MSI_CAPABILITY

0,1

0

PSU__PCIE__MSI_64BIT_ADDR_
CAPABLE

0,1

0

PSU__PCIE__MSI_MULTIPLE_MSG_
CAPABLE

<Select>,1 Vector,2 Vector,
4 Vector,8 Vector,16 Vector,
32 Vector

<Select>

PSU__PCIE__MSIX_CAPABILITY

0,1

0

PSU__PCIE__MSIX_TABLE_SIZE

NA

0

PSU__PCIE__MSIX_TABLE_OFFSET

NA

0

PSU__PCIE__MSIX_BAR_INDICATOR

NA

PSU__PCIE__MSIX_PBA_OFFSET

NA

0

PSU__PCIE__MSIX_PBA_BAR_
INDICATOR

NA

PCIE Related

Parameters

(continued)

PSU__PCIE__BRIDGE_BAR_INDICATOR

<Select>,BAR 0,BAR 1,BAR 2,
BAR 3,BAR 4,BAR 5

<Select>

PSU_IMPORT_BOARD_PRESET

NA

Isolation & protection related parameters

PSU__PROTECTION__SUBSYSTEMS

PMU Firmware: PU

PSU__PROTECTION__MASTERS_TZ

None

PSU__PROTECTION__MASTERS

See Table: PSU__PROTECTION__MASTERS Default Values
for values

PSU__PROTECTION__DDR_SEGMENTS

None

PSU__PROTECTION__OCM_SEGMENTS

None

PSU__PROTECTION__LPD_SEGMENTS

None

PSU__PROTECTION__FPD_SEGMENTS

None

PSU__PROTECTION__DEBUG

1

PSU__PROTECTION__SLAVES

See Table: PSU__PROTECTION__SLAVES
for values

PSU__PROTECTION__PRESUBSYSTEMS

None

PSU__PROTECTION__ENABLE

False

PSU__PROTECTION__LOCK_UNUSED_SEGMENTS

0

Internal Parameter

PSU__EP__IP

0,1

0

PSU__ACTUAL__IP

0,1

1

Nand Related Parameters

PSU__NAND__PERIPHERAL__IO

<Select>,MIO 13 .. 25

<Select>

PSU__NAND__PERIPHERAL__ENABLE

0,1

0

PSU__NAND__READY_BUSY__ENABLE

0,1

0

PSU__NAND__READY_BUSY__IO

<Select>,MIO 10 .. 11,MIO 27 .. 28

<Select>

PSU__NAND__CHIP_ENABLE__ENABLE

0,1

0

PSU__NAND__CHIP_ENABLE__IO

<Select>,MIO 9,MIO 26

<Select>

PSU__NAND__DATA_STROBE__ENABLE

0,1

0

PSU__NAND__DATA_STROBE__IO

<Select>,MIO 12,MIO 32

<Select>

PSU__PJTAG__PERIPHERAL__ENABLE

0,1

0

PSU__PJTAG__PERIPHERAL__IO

<Select>,MIO 0 .. 3,
MIO 12 .. 15,MIO 26 .. 29,
MIO 38 .. 41,MIO 52 .. 55,
MIO 58 .. 61

<Select>

PMU related Parameters

PSU__PMU__PERIPHERAL__ENABLE

0,1

0

PSU__PMU__PERIPHERAL__IO

<Select>

<Select>

PSU__PMU__EMIO_GPI__ENABLE (4)

0,1

0

PSU__PMU__EMIO_GPO__ENABLE

0,1

0

PSU__PMU__GPI0__ENABLE

0,1

0

PSU__PMU__GPI1__ENABLE

0,1

0

PSU__PMU__GPI2__ENABLE

0,1

0

PSU__PMU__GPI3__ENABLE

0,1

0

PSU__PMU__GPI4__ENABLE

0,1

0

PSU__PMU__GPI5__ENABLE

0,1

0

PSU__PMU__GPO0__ENABLE

0,1

0

PSU__PMU__GPO1__ENABLE

0,1

0

PSU__PMU__GPO2__ENABLE

0,1

0

PSU__PMU__GPO3__ENABLE

0,1

0

PSU__PMU__GPO4__ENABLE

0,1

0

PSU__PMU__GPO5__ENABLE

0,1

0

PSU__PMU__GPI0__IO (5)

<Select>,MIO 26

<Select>

PSU__PMU__GPI1__IO

<Select>,MIO 27

<Select>

PSU__PMU__GPI2__IO

<Select>,MIO 28

<Select>

PSU__PMU__GPI3__IO

<Select>,MIO 29

<Select>

PSU__PMU__GPI4__IO

<Select>,MIO 30

<Select>

PSU__PMU__GPI5__IO

<Select>,MIO 31

<Select>

PSU__PMU__GPO0__IO (6)

<Select>,MIO 32

<Select>

PSU__PMU__GPO1__IO

<Select>,MIO 33

<Select>

PSU__PMU__GPO2__IO

<Select>,MIO 34

<Select>

PSU__PMU__GPO3__IO

<Select>,MIO 35

<Select>

PSU__PMU__GPO4__IO

<Select>,MIO 36

<Select>

PSU__PMU__GPO5__IO

<Select>,MIO 37

<Select>

CONFIG.PSU__PMU__AIBACK__ENABLE

0,1

0

CONFIG.PSU__PMU__PLERROR__ENABLE

0,1

0

CSU

PSU__CSU__PERIPHERAL__ENABLE

0,1

0

PSU__CSU__PERIPHERAL__IO

<Select>,MIO 18,MIO 19,
MIO 20,MIO 21,MIO 22,
MIO 23,MIO 24,MIO 25,
MIO 26,MIO 31,MIO 32,MIO 33

<Select>

QSPI Related Parameters

PSU__QSPI__PERIPHERAL__ENABLE

0,1

0

PSU__QSPI__PERIPHERAL__IO

<Select>,MIO 0 .. 5,MIO 0 .. 7,
MIO 0 .. 12

<Select>

PSU__QSPI__PERIPHERAL__MODE

<Select>,Single,Dual Stacked,
Dual Parallel

<Select>

PSU__QSPI__PERIPHERAL__DATA_MODE

<Select>,x1,x2,x4

<Select>

PSU__QSPI__GRP_FBCLK__ENABLE

0,1

0

PSU__QSPI__GRP_FBCLK__IO

<Select>,MIO 6

<Select>

SD Related Parameters

PSU__SD0__PERIPHERAL__ENABLE

0,1

0

PSU__SD0__PERIPHERAL__IO

<Select>,EMIO,
MIO 13 .. 16 21 22,
MIO 38 .. 44,MIO 64 .. 70,
MIO 13 .. 22,MIO 38 .. 48,
MIO 64 .. 74

<Select>

PSU__SD0__GRP_CD__ENABLE

0,1

0

PSU__SD0__GRP_CD__IO

<Select>,EMIO,MIO 24,
MIO 39,MIO 65

<Select>

PSU__SD0__GRP_POW__ENABLE

0,1

0

PSU__SD0__GRP_POW__IO

<Select>,EMIO,MIO 23,
MIO 49,MIO 75

<Select>

PSU__SD0__GRP_WP__ENABLE

0,1

0

PSU__SD0__GRP_WP__IO

<Select>,EMIO,MIO 25,
MIO 50,MIO 76

<Select>

PSU__SD0__SLOT_TYPE

<Select>,SD 2.0,SD 3.0, SD 3.0 AUTODIR, eMMC

<Select>

PSU__SD0__RESET__ENABLE

0,1

0

PSU__SD0__DATA_TRANSFER_MODE

<Select>,4Bit,8Bit

<Select>

SD Related Parameters (cont’d )

PSU__SD0__CLK_50_SDR_ITAP_DLY

0x0-0xb3

0x0

PSU__SD0__CLK_50_SDR_OTAP_DLY

0x0-0x2c

0x0

PSU__SD0__CLK_50_DDR_ITAP_DLY

0x0-0xb3

0x0

PSU__SD0__CLK_50_DDR_OTAP_DLY

0x0-0x2c

0x0

PSU__SD0__CLK_100_SDR_OTAP_DLY

0x0-0x2c

0x0

PSU__SD0__CLK_200_SDR_OTAP_DLY

0x0-0x2c

0x0

PSU__SD1__CLK_50_SDR_ITAP_DLY

0x0-0xb3

PSU__SD1__CLK_50_SDR_OTAP_DLY

0x0-0x2c

0x0

PSU__SD1__CLK_50_DDR_ITAP_DLY

0x0-0xb3

0x0

PSU__SD1__CLK_50_DDR_OTAP_DLY

0x0-0x2c

0x0

PSU__SD1__CLK_100_SDR_OTAP_DLY

0x0-0x2c

0x0

PSU__SD1__CLK_200_SDR_OTAP_DLY

0x0-0x2c

0x0

PSU__SD1__PERIPHERAL__ENABLE

0,1

0

PSU__SD1__PERIPHERAL__IO

<Select>,EMIO,MIO 39 .. 51,
MIO 46 .. 51,MIO 71 .. 76

<Select>

PSU__SD1__GRP_CD__ENABLE

0,1

0

PSU__SD1__GRP_CD__IO

<Select>,MIO 45,MIO 77,EMIO

<Select>

PSU__SD1__GRP_POW__ENABLE

0,1

0

PSU__SD1__GRP_POW__IO

<Select>,MIO 43,MIO 70,EMIO

<Select>

PSU__SD1__GRP_WP__ENABLE

0,1

0

PSU__SD1__GRP_WP__IO

<Select>,MIO 44,MIO 69,EMIO

<Select>

PSU__SD1__SLOT_TYPE

<Select>,SD 2.0,SD 3.0, SD 3.0 AUTODIR, eMMC

<Select>

PSU__SD1__RESET__ENABLE

0,1

0

PSU__SD1__DATA_TRANSFER_MODE

<Select>,4Bit,8Bit

<Select>

Internal Parameter

PSU__DEVICE_TYPE

EG,CG,EV

EG

SPI Related Parameters

PSU__SPI0__PERIPHERAL__ENABLE

0,1

0

PSU__SPI0__PERIPHERAL__IO

<Select>,EMIO,MIO 0 .. 5,
MIO 12 .. 17,MIO 26 .. 31,
MIO 38 .. 43,MIO 52 .. 57,
MIO 64 .. 69

<Select>

PSU__SPI0__GRP_SS0__ENABLE

0,1

0

PSU__SPI0__GRP_SS0__IO

<Select>,MIO 3,MIO 15,
MIO 29,MIO 41,MIO 55,
MIO 67,EMIO

<Select>

PSU__SPI0__GRP_SS1__ENABLE

0,1

0

PSU__SPI0__GRP_SS1__IO

<Select>,MIO 2,MIO 14,
MIO 28,MIO 40,MIO 54,
MIO 66,EMIO

<Select>

PSU__SPI0__GRP_SS2__ENABLE

0,1

0

PSU__SPI0__GRP_SS2__IO

<Select>,MIO 1,MIO 13,
MIO 27,MIO 39,MIO 53,
MIO 65,EMIO

<Select>

PSU__SPI1__PERIPHERAL__ENABLE

0,1

0

PSU__SPI1__PERIPHERAL__IO

<Select>,EMIO,MIO 6 .. 11,
MIO 18 .. 23,
MIO 32 .. 37,MIO 44 .. 49,
MIO 58 .. 63,MIO 70 .. 75

<Select>

PSU__SPI1__GRP_SS0__ENABLE

0,1

0

PSU__SPI1__GRP_SS0__IO

<Select>,MIO 9,MIO 21,
MIO 35,MIO 47,MIO 61,
MIO 73,EMIO

<Select>

PSU__SPI1__GRP_SS1__ENABLE

0,1

0

PSU__SPI1__GRP_SS1__IO

<Select>,MIO 8,MIO 20,
MIO 34,MIO 46,MIO 60,
MIO 72,EMIO

<Select>

PSU__SPI1__GRP_SS2__ENABLE

0,1

0

PSU__SPI1__GRP_SS2__IO

<Select>,MIO 7,MIO 19,
MIO 33,MIO 45,MIO 59,
MIO 71,EMIO

<Select>

PSU__SPI0_LOOP_SPI1__ENABLE

0,1

0

SWDT Related parameters

PSU__SWDT0__PERIPHERAL__ENABLE

0,1

0

PSU__SWDT0__CLOCK__ENABLE

0,1

0

PSU__SWDT0__RESET__ENABLE

0,1

0

PSU__SWDT0__PERIPHERAL__IO

NA

NA

PSU__SWDT0__CLOCK__IO

<Select>,EMIO,MIO 6,MIO 10,
MIO 18,MIO 22,MIO 30,
MIO 34,MIO 42,MIO 46,
MIO 50,MIO 62,MIO 66,
MIO 70,MIO 74

<Select>

PSU__SWDT0__RESET__IO

<Select>,EMIO,MIO 7,MIO 11,
MIO 19,MIO 23,MIO 31,
MIO 35,MIO 43,MIO 47,
MIO 51,MIO 63,MIO 67,
MIO 71,MIO 75

<Select>

PSU__SWDT1__PERIPHERAL__ENABLE

0,1

0

PSU__SWDT1__CLOCK__ENABLE

0,1

0

PSU__SWDT1__RESET__ENABLE

0,1

0

PSU__SWDT1__PERIPHERAL__IO

NA

NA

PSU__SWDT1__CLOCK__IO

<Select>,EMIO,MIO 4,MIO 8,
MIO 16,MIO 20,MIO 24,
MIO 32,MIO 36,MIO 44,
MIO 48,MIO 56,MIO 64,
MIO 68,MIO 72

<Select>

PSU__SWDT1__RESET__IO

<Select>,EMIO,MIO 5,MIO 9,
MIO 17,MIO 21,MIO 25,
MIO 33,MIO 37,MIO 45,
MIO 49,MIO 57,MIO 65,
MIO 69,MIO 73

<Select>

UART Baud rate

PSU__UART0__BAUD_RATE

<Select>,110,300,1200,2400,4800,9600,19200,38400,57600,115200,
128000,230400,460800,921600

<Select>

Trace Related Parameters

PSU__TRACE__PERIPHERAL__ENABLE

0,1

0

PSU__TRACE__PERIPHERAL__IO

<Select>,MIO 0 .. 17,
MIO 26 .. 43,MIO 52 .. 69,EMIO

<Select>

PSU__TRACE__WIDTH

<Select>,2Bit,4Bit,8Bit,16Bit,32Bit

<Select>

PSU__TRACE__INTERNAL_WIDTH

2,4,8,16,32

32

TTC Related Parameters

PSU__TTC0__PERIPHERAL__ENABLE

0,1

0

PSU__TTC0__CLOCK__ENABLE

0,1

0

PSU__TTC0__WAVEOUT__ENABLE

0,1

0

PSU__TTC0__CLOCK__IO

<Select>,EMIO,MIO 6,MIO 14,
MIO 22,MIO 30,MIO 38,
MIO 46,MIO 54,MIO 62,MIO 70

<Select>

PSU__TTC0__WAVEOUT__IO

<Select>,EMIO,MIO 7,MIO 15,
MIO 23,MIO 31,MIO 39,
MIO 47,MIO 55,MIO 63,MIO 71

<Select>

PSU__TTC0__PERIPHERAL__IO

NA

NA

PSU__TTC1__PERIPHERAL__ENABLE

0,1

0

PSU__TTC1__PERIPHERAL__IO

NA

NA

UART Baud rate

PSU__UART1__BAUD_RATE

<Select>,110,300,1200,2400,4800,9600,19200,38400,57600,115200,
128000,230400,460800,921600

<Select>

TTC Related Parameters

PSU__TTC1__CLOCK__ENABLE

0,1

0

PSU__TTC1__WAVEOUT__ENABLE

0,1

0

PSU__TTC1__CLOCK__IO

<Select>,EMIO,MIO 4,MIO 12,
MIO 20,MIO 28,MIO 36,MIO 44,MIO 52,MIO 60,MIO 68

<Select>

PSU__TTC1__WAVEOUT__IO

<Select>,EMIO,MIO 5,MIO 13,
MIO 21,MIO 29,MIO 37,
MIO 45,MIO 53,MIO 61,MIO 69

<Select>

PSU__TTC2__PERIPHERAL__ENABLE

0,1

0

PSU__TTC2__PERIPHERAL__IO

NA

NA

PSU__TTC2__CLOCK__ENABLE

0,1

0

PSU__TTC2__WAVEOUT__ENABLE

0,1

0

PSU__TTC2__CLOCK__IO

<Select>,EMIO,MIO 2,MIO 10,
MIO 18,MIO 26,MIO 34,
MIO 42,MIO 50,MIO 58,MIO 66

<Select>

PSU__TTC2__WAVEOUT__IO

<Select>,EMIO,MIO 3,MIO 11,
MIO 19,MIO 27,MIO 35,
MIO 43,MIO 51,MIO 59,MIO 67

<Select>

PSU__TTC3__PERIPHERAL__ENABLE

0,1

0

PSU__TTC3__PERIPHERAL__IO

NA

NA

PSU__TTC3__CLOCK__ENABLE

0,1

0

PSU__TTC3__WAVEOUT__ENABLE

0,1

0

TTC Related

Parameters

(continued)

PSU__TTC3__CLOCK__IO

<Select>,EMIO,MIO 0,MIO 8,MIO 16,MIO 24,MIO 32,MIO 40,MIO 48,MIO 56,MIO 64

<Select>

PSU__TTC3__WAVEOUT__IO

<Select>,EMIO,MIO 1,MIO 9,MIO 17,MIO 25,MIO 33,MIO 41,MIO 49,MIO 57,MIO 65

<Select>

DDR Related Parameters

PSU__DDRC__AL

0

PSU__DDRC__BANK_ADDR_COUNT

3

PSU__DDRC__BUS_WIDTH

32 Bit,64 Bit

64 Bit

DDR Related Parameters

(Continued)

PSU__DDRC__CL

NA

7

PSU__DDRC__CLOCK_STOP_EN

0,1

0

PSU__DDRC__COL_ADDR_COUNT

10

PSU__DDRC__RANK_ADDR_COUNT

0

PSU__DDRC__CWL

NA

7

PSU__DDRC__BG_ADDR_COUNT

1.000000,2.000000

NA

PSU__DDRC__DEVICE_CAPACITY

512 MBits,1024 MBits,2048 MBits,4096 MBits,8192 MBits

2048 MBits

PSU__DDRC__DRAM_WIDTH

8 Bits,16 Bits

8 Bits

PSU__DDRC__ECC

Disabled,Enabled

Disabled

PSU__DDRC__ECC_SCRUB

0,1

0

PSU__DDRC__ENABLE

0,1

1

PSU__DDRC__FREQ_MHZ

-2,-1

1

PSU__DDRC__HIGH_TEMP

<Select>

<Select>

PSU__DDRC__MEMORY_TYPE

LPDDR 3,DDR 3,
DDR 3 (Low Voltage),DDR 4,
LPDDR 4

DDR 4

PSU__DDRC__PARTNO

<Select>

<Select>

PSU__DDRC__ROW_ADDR_COUNT

-2,-1

15

PSU__DDRC__SPEED_BIN

DDR3_800D,DDR3_800E,
DDR3_1066E,DDR3_1066F,
DDR3_1066G,DDR3_1333F,
DDR3_1333G,DDR3_1333H,
DDR3_1333J,DDR3_1600G,
DDR3_1600H,DDR3_1600J,
DDR3_1600K,DDR3_1866J,
DDR3_1866K,DDR3_1866L,
DDR3_1866M,DDR3_2133N

DDR4_1600J

PSU__DDRC__T_FAW

-0.1,100

35

PSU__DDRC__T_RAS_MIN

-0.1,100

35

PSU__DDRC__T_RC

-0.1,100

47.5

DDR Related Parameters

(continued)

PSU__DDRC__T_RCD

-2,-1

10

PSU__DDRC__T_RP

-0.1,100

10

PSU__DDRC__TRAIN_DATA_EYE

0,1

1

PSU__DDRC__TRAIN_READ_GATE

0,1

1

PSU__DDRC__TRAIN_WRITE_LEVEL

0,1

1

PSU__DDRC__VREF

0,1

1

PSU__DDRC__VIDEO_BUFFER_SIZE

0,1,2,4,8,16,32

0

PSU__DDRC__BRC_MAPPING

ROW_BANK_COL,BANK_ROW_COL

ROW_BANK_COL

PSU__DDRC__DIMM_ADDR_MIRROR

0,1

0

PSU__DDRC__STATIC_RD_MODE

0,1

0

PSU__DDRC__DDR4_MAXPWR_SAVING_EN

0,1

NA

PSU__DDRC__PWR_DOWN_EN

0,1

0

PSU__DDRC__DEEP_PWR_DOWN_EN

<Select>,0,1

<Select>

PSU__DDRC__PLL_BYPASS

0,1

0

PSU__DDRC__DDR4_T_REF_MODE

0,1

NA

PSU__DDRC__DDR4_T_REF_RANGE

Normal (0-85),High (95 Max)

NA

PSU__DDRC__PHY_DBI_MODE

0,1

0

PSU__DDRC__DM_DBI

NO_DM_NO_DBI,
NO_DM_DBI_RD_WR,NO_DM_DBI_RD,
NO_DM_DBI_WR,DM_DBI_RD_WR,DM_DBI_RD,DM_DBI_WR,DM_NO_DBI

DM_NO_
DBI

PSU__DDRC__COMPONENTS

Components,UDIMM,RDIMM

Components

PSU__DDRC__PARITY_ENABLE

0,1

NA

PSU__DDRC__DDR4_CAL_MODE_
ENABLE

0,1

NA

PSU__DDRC__DDR4_CRC_CONTROL

0,1

NA

PSU__DDRC__FGRM

1X,2X,4X

1X

PSU__DDRC__VENDOR_PART

OTHERS,SAMSUNG,HYNIX

OTHERS

DDR Related Parameters

(continued)

PSU__DDRC__SB_TARGET

5-5-5,6-6-6,7-7-7,8-8-8,9-9-9,
10-10-10,11-11-11,12-12-12,
13-13-13,14-14-14,15-15-15,
16-16-16,18-18-18,NA

10-10-10

PSU__DDRC__LP_ASR

manual normal,
manual reduced,
manual extended,
auto self refresh

manual normal

PSU__DDRC__DDR4_ADDR_MAPPING

0,1

NA

PSU__DDRC__SELF_REF_ABORT

0,1

0

PSU__DDRC__DERATE_INT_D

<Select>

<Select>

PSU__DDRC__ADDR_MIRROR

0,NA,1

NA

PSU__DDRC__EN_2ND_CLK

0,1

0

PSU__DDRC__PER_BANK_REFRESH

0,1

0

PSU_DDR_RAM_HIGHADDR

NA

0x1FFFFFFF

CONFIG.PSU__DDR_SW_REFRESH_ENABLED

0,1

1

Full Power Domain ON

PSU__FP__POWER__ON

0,1

1

PL Power ON

PSU__PL__POWER__ON

0,1

1

OCM Bank
Power ON

PSU__OCM_BANK0__POWER__ON

0,1

1

PSU__OCM_BANK1__POWER__ON

0,1

1

PSU__OCM_BANK2__POWER__ON

0,1

1

PSU__OCM_BANK3__POWER__ON

0,1

1

TCM Power On

PSU__TCM0A__POWER__ON

0,1

1

PSU__TCM0B__POWER__ON

0,1

1

PSU__TCM1A__POWER__ON

0,1

1

PSU__TCM1B__POWER__ON

0,1

1

RPU Power ON

PSU__RPU__POWER__ON

0,1

1

PSU__L2_BANK0__POWER__ON

0,1

1

PSU__GPU_PP0__POWER__ON

0,1

1

PSU__GPU_PP1__POWER__ON

0,1

1

PSU__ACPU0__POWER__ON

0,1

1

PSU__ACPU1__POWER__ON

0,1

1

PSU__ACPU2__POWER__ON

0,1

1

PSU__ACPU3__POWER__ON

0,1

1

UART Related Parameters

PSU__UART0__PERIPHERAL__ENABLE

0,1

0

PSU__UART0__PERIPHERAL__IO

<Select>,EMIO,MIO 2 .. 3,
MIO 6 .. 7,MIO 10 .. 11,
MIO 14 .. 15,MIO 18 .. 19,
MIO 22 .. 23,MIO 26 .. 27,
MIO 30 .. 31,MIO 34 .. 35,
MIO 38 .. 39,MIO 42 .. 43,
MIO 46 .. 47,MIO 50 .. 51,
MIO 54 .. 55,MIO 58 .. 59,
MIO 62 .. 63,MIO 66 .. 67,
MIO 70 .. 71,MIO 74 .. 75

<Select>

PSU__UART0__MODEM__ENABLE

0,1

0

PSU__UART1__PERIPHERAL__ENABLE

0,1

0

UART Related Parameters

(continued)

PSU__UART1__PERIPHERAL__IO

<Select>,EMIO,MIO 0 .. 1,
MIO 4 .. 5,MIO 8 .. 9,
MIO 12 .. 13,MIO 16 .. 17,
MIO 20 .. 21,MIO 24 .. 25,
MIO 28 .. 29,MIO 32 .. 33,
MIO 36 .. 37,MIO 40 .. 41,
MIO 44 .. 45,MIO 48 .. 49,
MIO 52 .. 53,MIO 56 .. 57,
MIO 60 .. 61,MIO 64 .. 65,
MIO 68 .. 69,MIO 72 .. 73

<Select>

PSU__UART1__MODEM__ENABLE

0,1

0

PSU__UART0_LOOP_UART1__ENABLE

0,1

0

USB Related Parameters

PSU__USB0__PERIPHERAL__ENABLE

0,1

0

PSU__USB0__PERIPHERAL__IO

<Select>,MIO 52 .. 63

<Select>

PSU__USB1__PERIPHERAL__ENABLE

0,1

0

PSU__USB1__PERIPHERAL__IO

<Select>,MIO 64 .. 75

<Select>

PSU__USB3_0__PERIPHERAL__ENABLE

0,1

0

PSU__USB3_0__PERIPHERAL__IO

<Select>,GT Lane0,GT Lane1,
GT Lane2

<Select>

PSU__USB3_1__PERIPHERAL__ENABLE

0,1

0

PSU__USB3_1__PERIPHERAL__IO

<Select>,GT Lane3

<Select>

PSU__USB3_0__EMIO__ENABLE

0,1

0

PSU__USB2_0__EMIO__ENABLE

0,1

0

PSU__USB3_1__EMIO__ENABLE

0,1

0

PSU__USB2_1__EMIO__ENABLE

0,1

0

PS PL Interface related Parameters

PSU__USE__M_AXI_GP0

0,1

0

PSU__MAXIGP0__DATA_WIDTH

128,64,32

128

PSU__USE__M_AXI_GP1

0,1

0

PSU__MAXIGP1__DATA_WIDTH

128,64,32

128

PSU__USE__M_AXI_GP2

0,1

1

PSU__MAXIGP2__DATA_WIDTH

128,64,32

128

PSU__USE__S_AXI_ACP

0,1

0

PSU__USE__S_AXI_GP0

0,1

0

PSU__USE_DIFF_RW_CLK_GP0

0,1

0

PSU__SAXIGP0__DATA_WIDTH

128,64,32

128

PSU__USE__S_AXI_GP1

0,1

0

PSU__USE_DIFF_RW_CLK_GP1

0,1

0

PSU__SAXIGP1__DATA_WIDTH

128,64,32

128

PS PL Interface related Parameters

(continued)

PSU__USE__S_AXI_GP2

0,1

0

PSU__USE_DIFF_RW_CLK_GP2

0,1

0

PSU__SAXIGP2__DATA_WIDTH

128,64,32

128

PSU__USE__S_AXI_GP3

0,1

0

PSU__USE_DIFF_RW_CLK_GP3

0,1

0

PSU__SAXIGP3__DATA_WIDTH

128,64,32

128

PSU__USE__S_AXI_GP4

0,1

0

PSU__USE_DIFF_RW_CLK_GP4

0,1

0

PSU__SAXIGP4__DATA_WIDTH

128,64,32

128

PSU__USE__S_AXI_GP5

0,1

0

PSU__USE_DIFF_RW_CLK_GP5

0,1

0

PSU__SAXIGP5__DATA_WIDTH

128,64,32

128

PSU__USE__S_AXI_GP6

0,1

0

PSU__USE_DIFF_RW_CLK_GP6

0,1

0

PSU__SAXIGP6__DATA_WIDTH

128,64,32

128

PSU__USE__S_AXI_ACE

0,1

0

PSU__USE__FABRIC__RST

0,1

1

PSU__USB__RESET__MODE

Boot Pin, Shared MIO pin, Separate MIO pin, Disable

Boot pin

PSU__USB__RESET__POLARITY

Active Low, Active High

Active Low

PSU__USB0__RESET__ENABLE

0,1

0

PSU__USB0__RESET__IO

<Select>,MIO 0 ..77

<select>

PSU__USB1__RESET__ENABLE

0,1

0

PSU__USB1__RESET__IO

<Select>,MIO 0 .. 77

<select>

MIO Pin Properties like pull down, drive strength, direction and slew

PSU_MIO_0_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_0_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_0_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_0_SLEW

fast,slow

slow

PSU_MIO_0_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_1_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_1_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_1_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_1_SLEW

fast,slow

slow

PSU_MIO_1_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_2_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_2_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_2_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_2_SLEW

fast,slow

slow

PSU_MIO_2_DIRECTION

<Select>,in,out,inout

<Select>

MIO Pin Properties like pull down, drive strength, direction and slew

(continued)

PSU_MIO_3_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_3_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_3_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_3_SLEW

fast,slow

slow

PSU_MIO_3_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_4_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_4_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_4_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_4_SLEW

fast,slow

slow

PSU_MIO_4_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_5_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_5_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_5_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_5_SLEW

fast,slow

slow

PSU_MIO_5_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_6_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_6_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_6_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_6_SLEW

fast,slow

slow

PSU_MIO_6_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_7_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_7_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_7_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_7_SLEW

fast,slow

slow

PSU_MIO_7_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_8_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_8_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_8_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_8_SLEW

fast,slow

slow

PSU_MIO_8_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_9_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_9_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_9_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_9_SLEW

fast,slow

slow

MIO Pin Properties like pull down, drive strength, direction and slew

(continued)

PSU_MIO_9_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_10_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_10_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_10_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_10_SLEW

fast,slow

slow

PSU_MIO_10_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_11_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_11_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_11_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_11_SLEW

fast,slow

slow

PSU_MIO_11_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_12_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_12_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_12_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_12_SLEW

fast,slow

slow

PSU_MIO_12_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_13_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_13_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_13_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_13_SLEW

fast,slow

slow

PSU_MIO_13_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_14_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_14_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_14_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_14_SLEW

fast,slow

slow

PSU_MIO_14_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_15_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_15_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_15_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_15_SLEW

fast,slow

slow

PSU_MIO_15_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_16_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_16_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_16_INPUT_TYPE

cmos,schmitt

schmitt

MIO Pin Properties like pull down, drive strength, direction and slew

(continued)

PSU_MIO_16_SLEW

fast,slow

slow

PSU_MIO_16_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_17_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_17_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_17_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_17_SLEW

fast,slow

slow

PSU_MIO_17_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_18_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_18_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_18_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_18_SLEW

fast,slow

slow

PSU_MIO_18_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_19_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_19_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_19_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_19_SLEW

fast,slow

slow

PSU_MIO_19_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_20_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_20_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_20_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_20_SLEW

fast,slow

slow

PSU_MIO_20_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_21_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_21_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_21_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_21_SLEW

fast,slow

slow

PSU_MIO_21_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_22_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_22_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_22_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_22_SLEW

fast,slow

slow

PSU_MIO_22_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_23_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_23_DRIVE_STRENGTH

2,4,8,12

12

MIO Pin Properties like pull down, drive strength, direction and slew

(continued)

PSU_MIO_23_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_23_SLEW

fast,slow

slow

PSU_MIO_23_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_24_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_24_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_24_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_24_SLEW

fast,slow

slow

PSU_MIO_24_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_25_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_25_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_25_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_25_SLEW

fast,slow

slow

PSU_MIO_25_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_26_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_26_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_26_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_26_SLEW

fast,slow

slow

PSU_MIO_26_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_27_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_27_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_27_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_27_SLEW

fast,slow

slow

PSU_MIO_27_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_28_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_28_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_28_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_28_SLEW

fast,slow

slow

PSU_MIO_28_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_29_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_29_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_29_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_29_SLEW

fast,slow

slow

PSU_MIO_29_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_30_PULLUPDOWN

pulldown,pullup,disable

pullup

MIO Pin Properties like pull down, drive strength, direction and slew

(continued)

PSU_MIO_30_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_30_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_30_SLEW

fast,slow

slow

PSU_MIO_30_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_31_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_31_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_31_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_31_SLEW

fast,slow

slow

PSU_MIO_31_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_32_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_32_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_32_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_32_SLEW

fast,slow

slow

PSU_MIO_32_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_33_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_33_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_33_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_33_SLEW

fast,slow

slow

PSU_MIO_33_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_34_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_34_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_34_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_34_SLEW

fast,slow

slow

PSU_MIO_34_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_35_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_35_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_35_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_35_SLEW

fast,slow

slow

PSU_MIO_35_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_36_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_36_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_36_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_36_SLEW

fast,slow

slow

PSU_MIO_36_DIRECTION

<Select>,in,out,inout

<Select>

MIO Pin Properties like pull down, drive strength, direction and slew

(continued)

PSU_MIO_37_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_37_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_37_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_37_SLEW

fast,slow

slow

PSU_MIO_37_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_38_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_38_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_38_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_38_SLEW

fast,slow

slow

PSU_MIO_38_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_39_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_39_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_39_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_39_SLEW

fast,slow

slow

PSU_MIO_39_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_40_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_40_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_40_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_40_SLEW

fast,slow

slow

PSU_MIO_40_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_41_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_41_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_41_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_41_SLEW

fast,slow

slow

PSU_MIO_41_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_42_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_42_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_42_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_42_SLEW

fast,slow

slow

PSU_MIO_42_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_43_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_43_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_43_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_43_SLEW

fast,slow

slow

MIO Pin Properties like pull down, drive strength, direction and slew

(continued)

PSU_MIO_43_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_44_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_44_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_44_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_44_SLEW

fast,slow

slow

PSU_MIO_44_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_45_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_45_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_45_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_45_SLEW

fast,slow

slow

PSU_MIO_45_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_46_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_46_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_46_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_46_SLEW

fast,slow

slow

PSU_MIO_46_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_47_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_47_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_47_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_47_SLEW

fast,slow

slow

PSU_MIO_47_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_48_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_48_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_48_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_48_SLEW

fast,slow

slow

PSU_MIO_48_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_49_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_49_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_49_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_49_SLEW

fast,slow

slow

PSU_MIO_49_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_50_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_50_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_50_INPUT_TYPE

cmos,schmitt

schmitt

MIO Pin Properties like pull down, drive strength, direction and slew

(continued)

PSU_MIO_50_SLEW

fast,slow

slow

PSU_MIO_50_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_51_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_51_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_51_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_51_SLEW

fast,slow

slow

PSU_MIO_51_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_52_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_52_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_52_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_52_SLEW

fast,slow

slow

PSU_MIO_52_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_53_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_53_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_53_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_53_SLEW

fast,slow

slow

PSU_MIO_53_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_54_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_54_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_54_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_54_SLEW

fast,slow

slow

PSU_MIO_54_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_55_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_55_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_55_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_55_SLEW

fast,slow

slow

PSU_MIO_55_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_56_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_56_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_56_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_56_SLEW

fast,slow

slow

PSU_MIO_56_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_57_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_57_DRIVE_STRENGTH

2,4,8,12

12

MIO Pin Properties like pull down, drive strength, direction and slew

(continued)

PSU_MIO_57_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_57_SLEW

fast,slow

slow

PSU_MIO_57_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_58_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_58_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_58_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_58_SLEW

fast,slow

slow

PSU_MIO_58_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_59_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_59_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_59_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_59_SLEW

fast,slow

slow

PSU_MIO_59_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_60_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_60_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_60_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_60_SLEW

fast,slow

slow

PSU_MIO_60_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_61_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_61_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_61_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_61_SLEW

fast,slow

slow

PSU_MIO_61_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_62_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_62_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_62_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_62_SLEW

fast,slow

slow

PSU_MIO_62_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_63_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_63_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_63_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_63_SLEW

fast,slow

slow

PSU_MIO_63_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_64_PULLUPDOWN

pulldown,pullup,disable

pullup

MIO Pin Properties like pull down, drive strength, direction and slew

(continued)

PSU_MIO_64_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_64_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_64_SLEW

fast,slow

slow

PSU_MIO_64_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_65_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_65_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_65_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_65_SLEW

fast,slow

slow

PSU_MIO_65_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_66_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_66_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_66_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_66_SLEW

fast,slow

slow

PSU_MIO_66_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_67_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_67_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_67_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_67_SLEW

fast,slow

slow

PSU_MIO_67_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_68_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_68_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_68_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_68_SLEW

fast,slow

slow

PSU_MIO_68_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_69_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_69_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_69_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_69_SLEW

fast,slow

slow

PSU_MIO_69_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_70_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_70_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_70_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_70_SLEW

fast,slow

slow

PSU_MIO_70_DIRECTION

<Select>,in,out,inout

<Select>

MIO Pin Properties like pull down, drive strength, direction and slew

(continued)

PSU_MIO_71_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_71_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_71_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_71_SLEW

fast,slow

slow

PSU_MIO_71_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_72_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_72_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_72_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_72_SLEW

fast,slow

slow

PSU_MIO_72_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_73_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_73_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_73_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_73_SLEW

fast,slow

slow

PSU_MIO_73_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_74_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_74_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_74_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_74_SLEW

fast,slow

slow

PSU_MIO_74_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_75_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_75_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_75_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_75_SLEW

fast,slow

slow

PSU_MIO_75_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_76_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_76_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_76_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_76_SLEW

fast,slow

slow

PSU_MIO_76_DIRECTION

<Select>,in,out,inout

<Select>

PSU_MIO_77_PULLUPDOWN

pulldown,pullup,disable

pullup

PSU_MIO_77_DRIVE_STRENGTH

2,4,8,12

12

PSU_MIO_77_INPUT_TYPE

cmos,schmitt

schmitt

PSU_MIO_77_SLEW

fast,slow

slow

PSU_MIO_77_DIRECTION

<Select>,in,out,inout

<Select>

Bank 0 Standard

PSU_BANK_0_IO_STANDARD

LVCMOS18,LVCMOS25,LVCMOS33

LVCMOS33

Bank 1 Standard

PSU_BANK_1_IO_STANDARD

LVCMOS18,LVCMOS25,LVCMOS33

LVCMOS33

Bank 2 Standard

PSU_BANK_2_IO_STANDARD

LVCMOS18,LVCMOS25,LVCMOS33

LVCMOS33

Bank 2 Standard

PSU_BANK_3_IO_STANDARD

LVCMOS18,LVCMOS25,LVCMOS33

LVCMOS33

Clocking related Parameters and Divisors

PSU__CRF_APB__APLL_CTRL__FRACDATA

0

PSU__CRF_APB__VPLL_CTRL__FRACDATA

0

PSU__CRF_APB__DPLL_CTRL__FRACDATA

0

PSU__CRL_APB__IOPLL_CTRL__
FRACDATA

0

PSU__CRL_APB__RPLL_CTRL__FRACDATA

0

PSU__CRF_APB__DPLL_CTRL__DIV2

0,1

1

PSU__CRF_APB__APLL_CTRL__DIV2

0,1

1

PSU__CRF_APB__VPLL_CTRL__DIV2

0,1

1

PSU__CRL_APB__IOPLL_CTRL__DIV2

0,1

1

PSU__CRL_APB__RPLL_CTRL__DIV2

0,1

1

PSU__CRF_APB__APLL_CTRL__FBDIV

72

PSU__CRF_APB__DPLL_CTRL__FBDIV

60

PSU__CRF_APB__VPLL_CTRL__FBDIV

90

PSU__CRF_APB__APLL_TO_LPD_CTRL__
DIVISOR0

3

PSU__CRF_APB__DPLL_TO_LPD_CTRL__
DIVISOR0

2

PSU__CRF_APB__VPLL_TO_LPD_CTRL__
DIVISOR0

3

PSU__CRF_APB__ACPU_CTRL__DIVISOR0

1

PSU__CRF_APB__DBG_TRACE_CTRL__
DIVISOR0

2

Display Port

PSU__DISPLAYPORT__PERIPHERAL__
ENABLE

0,1

0

PSU__DISPLAYPORT__LANE0__ENABLE

0,1

0

PSU__DISPLAYPORT__LANE0__IO

<Select>,GT Lane1,GT Lane3

<Select>

PSU__DISPLAYPORT__LANE1__ENABLE

0,1

0

PSU__DISPLAYPORT__LANE1__IO

<Select>,GT Lane0,GT Lane2

<Select>

Clocking related Parameters and Divisors

PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0

2

PSU__CRF_APB__APM_CTRL__DIVISOR0

1

PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0

5

PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1

1

PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0

64

PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1

1

PSU__CRF_APB__DP_STC_REF_CTRL__
DIVISOR0

6

PSU__CRF_APB__DP_STC_REF_CTRL__
DIVISOR1

10

PSU__CRF_APB__DDR_CTRL__DIVISOR0

3

PSU__CRF_APB__GPU_REF_CTRL__
DIVISOR0

2

PSU__CRF_APB__AFI0_REF_CTRL__
DIVISOR0

2

PSU__CRF_APB__AFI0_REF__ENABLE

0,1

0

PSU__CRF_APB__AFI1_REF_CTRL__
DIVISOR0

2

PSU__CRF_APB__AFI1_REF__ENABLE

0,1

0

PSU__CRF_APB__AFI2_REF_CTRL__
DIVISOR0

2

PSU__CRF_APB__AFI2_REF__ENABLE

0,1

0

PSU__CRF_APB__AFI3_REF_CTRL__
DIVISOR0

2

PSU__CRF_APB__AFI3_REF__ENABLE

0,1

0

PSU__CRF_APB__AFI4_REF_CTRL__
DIVISOR0

2

PSU__CRF_APB__AFI4_REF__ENABLE

0,1

0

PSU__CRF_APB__AFI5_REF_CTRL__
DIVISOR0

2

PSU__CRF_APB__AFI5_REF__ENABLE

0,1

0

PSU__CRF_APB__SATA_REF_CTRL__
DIVISOR0

5

SATA Related Parameters

PSU__SATA__PERIPHERAL__ENABLE

0,1

0

PSU__SATA__LANE0__ENABLE

0,1

0

PSU__SATA__LANE0__IO

<Select>,GT Lane0,GT Lane2

<Select>

PSU__SATA__LANE1__ENABLE

0,1

0

PSU__SATA__LANE1__IO

<Select>,GT Lane1,GT Lane3

<Select>

Clocking related Parameters and Divisors

PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0

6

PSU__CRL_APB__PL0_REF_CTRL__
DIVISOR0

15

PSU__CRL_APB__PL1_REF_CTRL__
DIVISOR0

4

PSU__CRL_APB__PL2_REF_CTRL__
DIVISOR0

4

PSU__CRL_APB__PL3_REF_CTRL__
DIVISOR0

4

PSU__CRL_APB__PL0_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__PL1_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__PL2_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__PL3_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__AMS_REF_CTRL__
DIVISOR0

30

PSU__CRL_APB__AMS_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0

15

PSU__CRL_APB__AFI6_REF_CTRL__
DIVISOR0

3

PSU__CRL_APB__AFI6__ENABLE

0,1

0

PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0

5

PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1

15

PSU__CRL_APB__USB3__ENABLE

0,1

0

PSU__CRF_APB__GDMA_REF_CTRL__
DIVISOR0

2

Clocking related Parameters and Divisors

(continued)

PSU__CRF_APB__DPDMA_REF_CTRL__
DIVISOR0

2

PSU__CRF_APB__TOPSW_MAIN_CTRL__
DIVISOR0

2

PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0

5

PSU__CRF_APB__GTGREF0_REF_CTRL__
DIVISOR0

-1

PSU__CRF_APB__GTGREF0__ENABLE

NA

NA

PSU__CRF_APB__DBG_TSTMP_CTRL__
DIVISOR0

2

PSU__CRL_APB__IOPLL_CTRL__FBDIV

90

PSU__CRL_APB__RPLL_CTRL__FBDIV

90

PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0

3

PSU__CRL_APB__RPLL_TO_FPD_CTRL__
DIVISOR0

3

PSU__CRL_APB__GEM0_REF_CTRL__
DIVISOR0

12

PSU__CRL_APB__GEM1_REF_CTRL__
DIVISOR0

12

PSU__CRL_APB__GEM2_REF_CTRL__
DIVISOR0

12

PSU__CRL_APB__GEM3_REF_CTRL__
DIVISOR0

12

PSU__CRL_APB__GEM0_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__GEM1_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__GEM2_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__GEM3_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__GEM_TSU_REF_CTRL__
DIVISOR0

4

PSU__CRL_APB__GEM_TSU_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0

6

Clocking related Parameters and Divisors

(continued)

PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1

1

PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0

6

PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1

1

PSU__CRL_APB__QSPI_REF_CTRL__
DIVISOR0

5

PSU__CRL_APB__QSPI_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__SDIO0_REF_CTRL__
DIVISOR0

7

PSU__CRL_APB__SDIO0_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__SDIO1_REF_CTRL__
DIVISOR0

7

PSU__CRL_APB__SDIO1_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__UART0_REF_CTRL__
DIVISOR0

15

PSU__CRL_APB__UART0_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__UART1_REF_CTRL__
DIVISOR0

15

PSU__CRL_APB__UART1_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__I2C0_REF_CTRL__
DIVISOR0

15

PSU__CRL_APB__I2C0_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__I2C1_REF_CTRL__
DIVISOR0

15

PSU__CRL_APB__I2C1_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__SPI0_REF_CTRL__
DIVISOR0

7

PSU__CRL_APB__SPI0_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__SPI1_REF_CTRL__
DIVISOR0

7

Clocking related Parameters and Divisors

(continued)

PSU__CRL_APB__SPI1_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__CAN0_REF_CTRL__
DIVISOR0

15

PSU__CRL_APB__CAN0_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__CAN1_REF_CTRL__
DIVISOR0

15

PSU__CRL_APB__CAN1_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__DEBUG_R5_ATCLK_
CTRL__DIVISOR0

6

PSU__CRL_APB__CPU_R5_CTRL__
DIVISOR0

3

PSU__CRL_APB__OCM_MAIN_CTRL__
DIVISOR0

3

PSU__CRL_APB__IOU_SWITCH_CTRL__
DIVISOR0

6

PSU__CRL_APB__CSU_PLL_CTRL__
DIVISOR0

3

PSU__CRL_APB__PCAP_CTRL__DIVISOR0

6

PSU__CRL_APB__LPD_LSBUS_CTRL__
DIVISOR0

15

PSU__CRL_APB__LPD_SWITCH_CTRL__
DIVISOR0

3

PSU__CRL_APB__DBG_LPD_CTRL__
DIVISOR0

6

PSU__CRL_APB__NAND_REF_CTRL__
DIVISOR0

15

PSU__CRL_APB__NAND_REF_CTRL__
DIVISOR1

1

PSU__CRL_APB__ADMA_REF_CTRL__
DIVISOR0

3

PSU__CRF_APB__APLL_CTRL__SRCSEL

PSS_REF_CLK

PSS_REF_CLK

PSU__CRF_APB__DPLL_CTRL__SRCSEL

PSS_REF_CLK

PSS_REF_CLK

PSU__CRF_APB__VPLL_CTRL__SRCSEL

PSS_REF_CLK

PSS_REF_CLK

PSU__CRF_APB__ACPU_CTRL__SRCSEL

APLL,DPLL,VPLL

APLL

Clocking related Parameters and Divisors

(continued)

PSU__CRF_APB__DBG_TRACE_CTRL__
SRCSEL

IOPLL,DPLL,APLL

IOPLL

PSU__CRF_APB__DBG_FPD_CTRL__
SRCSEL

IOPLL,DPLL,APLL

IOPLL

PSU__CRF_APB__APM_CTRL__SRCSEL

<Select>

<Select>

PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL

VPLL,DPLL,RPLL

VPLL

PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL

VPLL,DPLL,RPLL

VPLL

PSU__CRF_APB__DP_STC_REF_CTRL__
SRCSEL

VPLL,DPLL,RPLL,
FMIO_AUDIO_STREAM_CLK

VPLL

PSU__CRF_APB__DDR_CTRL__SRCSEL

DPLL,VPLL

DPLL

PSU__CRF_APB__GPU_REF_CTRL__
SRCSEL

IOPLL,VPLL,DPLL

DPLL

PSU__CRF_APB__AFI0_REF_CTRL__
SRCSEL

APLL,VPLL,DPLL

DPLL

PSU__CRF_APB__AFI1_REF_CTRL__
SRCSEL

APLL,VPLL,DPLL

DPLL

PSU__CRF_APB__AFI2_REF_CTRL__
SRCSEL

APLL,VPLL,DPLL

DPLL

PSU__CRF_APB__AFI3_REF_CTRL__
SRCSEL

APLL,VPLL,DPLL

DPLL

PSU__CRF_APB__AFI4_REF_CTRL__
SRCSEL

APLL,VPLL,DPLL

DPLL

PSU__CRF_APB__AFI5_REF_CTRL__
SRCSEL

APLL,VPLL,DPLL

DPLL

PSU__CRF_APB__SATA_REF_CTRL__
SRCSEL

APLL,IOPLL,DPLL

IOPLL

PSU__CRF_APB__PCIE_REF_CTRL__
SRCSEL

IOPLL,RPLL,DPLL

IOPLL

PSU__CRL_APB__PL0_REF_CTRL__SRCSEL

DPLL,IOPLL,RPLL

RPLL

PSU__CRL_APB__PL1_REF_CTRL__SRCSEL

DPLL,IOPLL,RPLL

RPLL

PSU__CRL_APB__PL2_REF_CTRL__SRCSEL

DPLL,IOPLL,RPLL

RPLL

PSU__CRL_APB__PL3_REF_CTRL__SRCSEL

DPLL,IOPLL,RPLL

RPLL

PSU__CRF_APB__GDMA_REF_CTRL__
SRCSEL

APLL,VPLL,DPLL

APLL

PSU__CRF_APB__DPDMA_REF_CTRL__
SRCSEL

APLL,VPLL,DPLL

APLL

PSU__CRF_APB__TOPSW_MAIN_CTRL__
SRCSEL

APLL,VPLL,DPLL

DPLL

Clocking related Parameters and Divisors

(continued)

PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL

APLL,IOPLL,DPLL

IOPLL

PSU__CRF_APB__GTGREF0_REF_CTRL__
SRCSEL

NA

NA

PSU__CRF_APB__DBG_TSTMP_CTRL__
SRCSEL

APLL,DPLL,IOPLL

IOPLL

PSU__CRL_APB__IOPLL_CTRL__SRCSEL

PSS_REF_CLK

PSS_REF_CLK

PSU__CRL_APB__RPLL_CTRL__SRCSEL

PSS_REF_CLK

PSS_REF_CLK

PSU__CRL_APB__GEM0_REF_CTRL__
SRCSEL

DPLL,IOPLL,RPLL

IOPLL

PSU__CRL_APB__GEM1_REF_CTRL__
SRCSEL

DPLL,IOPLL,RPLL

IOPLL

PSU__CRL_APB__GEM2_REF_CTRL__
SRCSEL

DPLL,IOPLL,RPLL

IOPLL

PSU__CRL_APB__GEM3_REF_CTRL__
SRCSEL

DPLL,IOPLL,RPLL

IOPLL

PSU__CRL_APB__GEM_TSU_REF_CTRL__
SRCSEL

IOPLL,RPLL,DPLL

RPLL

PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL

DPLL,IOPLL,RPLL

IOPLL

PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL

DPLL,IOPLL,RPLL

IOPLL

PSU__CRL_APB__QSPI_REF_CTRL__
SRCSEL

DPLL,IOPLL,RPLL

IOPLL

PSU__CRL_APB__SDIO0_REF_CTRL__
SRCSEL

VPLL,IOPLL,RPLL

RPLL

PSU__CRL_APB__SDIO1_REF_CTRL__
SRCSEL

VPLL,IOPLL,RPLL

RPLL

PSU__CRL_APB__UART0_REF_CTRL__
SRCSEL

DPLL,IOPLL,RPLL

IOPLL

PSU__CRL_APB__UART1_REF_CTRL__
SRCSEL

DPLL,IOPLL,RPLL

IOPLL

PSU__CRL_APB__I2C0_REF_CTRL__
SRCSEL

DPLL,IOPLL,RPLL

IOPLL

PSU__CRL_APB__I2C1_REF_CTRL__
SRCSEL

DPLL,IOPLL,RPLL

IOPLL

PSU__CRL_APB__SPI0_REF_CTRL__
SRCSEL

DPLL,IOPLL,RPLL

RPLL

Clocking related Parameters and Divisors

(continued)

PSU__CRL_APB__SPI1_REF_CTRL__
SRCSEL

DPLL,IOPLL,RPLL

RPLL

PSU__CRL_APB__CAN0_REF_CTRL__
SRCSEL

DPLL,IOPLL,RPLL

IOPLL

PSU__CRL_APB__CAN1_REF_CTRL__
SRCSEL

DPLL,IOPLL,RPLL

IOPLL

PSU__CRL_APB__DEBUG_R5_ATCLK_
CTRL__SRCSEL

RPLL,IOPLL,DPLL

RPLL

PSU__CRL_APB__CPU_R5_CTRL__SRCSEL

IOPLL,RPLL,DPLL

RPLL

PSU__CRL_APB__OCM_MAIN_CTRL__
SRCSEL

IOPLL,RPLL,DPLL

IOPLL

PSU__CRL_APB__IOU_SWITCH_CTRL__
SRCSEL

IOPLL,RPLL,DPLL

RPLL

PSU__CRL_APB__CSU_PLL_CTRL__
SRCSEL

DPLL,IOPLL,RPLL,SysOsc

SysOsc

PSU__CRL_APB__PCAP_CTRL__SRCSEL

DPLL,IOPLL,RPLL

RPLL

PSU__CRL_APB__LPD_LSBUS_CTRL__
SRCSEL

IOPLL,RPLL,DPLL

IOPLL

PSU__CRL_APB__LPD_SWITCH_CTRL__
SRCSEL

IOPLL,RPLL,DPLL

IOPLL

PSU__CRL_APB__DBG_LPD_CTRL__
SRCSEL

IOPLL,RPLL,DPLL

IOPLL

PSU__CRL_APB__NAND_REF_CTRL__
SRCSEL

DPLL,IOPLL,RPLL

IOPLL

PSU__CRL_APB__ADMA_REF_CTRL__
SRCSEL

RPLL,IOPLL,DPLL

IOPLL

PSU__CRL_APB__DLL_REF_CTRL__
SRCSEL

IOPLL,RPLL

IOPLL

PSU__CRL_APB__AMS_REF_CTRL__
SRCSEL

IOPLL,RPLL,DPLL

IOPLL

PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL

RPLL,IOPLL,DPLL

IOPLL

PSU__CRL_APB__AFI6_REF_CTRL__
SRCSEL

RPLL,IOPLL,DPLL

IOPLL

PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL

IOPLL,RPLL,DPLL

IOPLL

PSU__IOU_SLCR__WDT_CLK_SEL__
SELECT

APB,External

APB

PSU__FPD_SLCR__WDT_CLK_SEL__
SELECT

APB,External

APB

Clocking related Parameters and Divisors

(continued)

PSU__IOU_SLCR__IOU_TTC_APB_CLK__
TTC0_SEL

APB,CPU_R5,PSS_REF_CLK

APB

PSU__IOU_SLCR__IOU_TTC_APB_CLK__
TTC1_SEL

APB,CPU_R5,PSS_REF_CLK

APB

PSU__IOU_SLCR__IOU_TTC_APB_CLK__
TTC2_SEL

APB,CPU_R5,PSS_REF_CLK

APB

PSU__IOU_SLCR__IOU_TTC_APB_CLK__
TTC3_SEL

APB,CPU_R5,PSS_REF_CLK

APB

PSU__CRF_APB__APLL_FRAC_CFG__
ENABLED

0,1

0

PSU__CRF_APB__VPLL_FRAC_CFG__
ENABLED

0,1

0

PSU__CRF_APB__DPLL_FRAC_CFG__
ENABLED

0,1

0

PSU__CRL_APB__IOPLL_FRAC_CFG__
ENABLED

0,1

0

PSU__CRL_APB__RPLL_FRAC_CFG__
ENABLED

0,1

0

PSU__OVERRIDE__BASIC_CLOCK

0,1

0

PSU__PL_CLK0_BUF

FALSE,TRUE

TRUE

PSU__PL_CLK1_BUF

FALSE,TRUE

FALSE

PSU__PL_CLK2_BUF

FALSE,TRUE

FALSE

PSU__PL_CLK3_BUF

FALSE,TRUE

FALSE

PSU__CRF_APB__APLL_CTRL__FRACFREQ

27.138

PSU__CRF_APB__VPLL_CTRL__FRACFREQ

27.138

PSU__CRF_APB__DPLL_CTRL__FRACFREQ

27.138

PSU__CRL_APB__IOPLL_CTRL__
FRACFREQ

27.138

PSU__CRL_APB__RPLL_CTRL__FRACFREQ

27.138

PSU__IOU_SLCR__TTC0__ACT_FREQMHZ

0.000000,600.000000

100

PSU__IOU_SLCR__TTC1__ACT_FREQMHZ

0.000000,600.000000

100

PSU__IOU_SLCR__TTC2__ACT_FREQMHZ

0.000000,600.000000

100

PSU__IOU_SLCR__TTC3__ACT_FREQMHZ

600.000000,0.000000

100

PSU__IOU_SLCR__WDT0__ACT_
FREQMHZ

0.000000,100.000000

100

PSU__FPD_SLCR__WDT1__ACT_
FREQMHZ

100

Clocking related Parameters and Divisors

(continued)

PSU__CRF_APB__ACPU_CTRL__ACT_
FREQMHZ

1199.988

PSU__CRF_APB__DBG_TRACE_CTRL__
ACT_FREQMHZ

249.997

PSU__CRF_APB__DBG_FPD_CTRL__ACT_
FREQMHZ

249.997

PSU__CRF_APB__APM_CTRL__ACT_
FREQMHZ

1

PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ

320

PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ

25

PSU__CRF_APB__DP_STC_REF_CTRL__
ACT_FREQMHZ

27

PSU__CRF_APB__DDR_CTRL__ACT_
FREQMHZ

374.996

PSU__DDR__INTERFACE__FREQMHZ

0.000000,600.000000

400.00

PSU__CRF_APB__GPU_REF_CTRL__ACT_
FREQMHZ

499.995

PSU__CRF_APB__AFI0_REF_CTRL__ACT_
FREQMHZ

667

PSU__CRF_APB__AFI1_REF_CTRL__ACT_
FREQMHZ

667

PSU__CRF_APB__AFI2_REF_CTRL__ACT_
FREQMHZ

667

PSU__CRF_APB__AFI3_REF_CTRL__ACT_
FREQMHZ

667

PSU__CRF_APB__AFI4_REF_CTRL__ACT_
FREQMHZ

667

PSU__CRF_APB__AFI5_REF_CTRL__ACT_
FREQMHZ

667

PSU__CRF_APB__SATA_REF_CTRL__ACT_
FREQMHZ

250

PSU__CRF_APB__PCIE_REF_CTRL__ACT_
FREQMHZ

250

PSU__CRL_APB__PL0_REF_CTRL__ACT_
FREQMHZ

99.999

PSU__CRL_APB__PL1_REF_CTRL__ACT_
FREQMHZ

100

PSU__CRL_APB__PL2_REF_CTRL__ACT_
FREQMHZ

100

Clocking related Parameters and Divisors

(continued)

PSU__CRL_APB__PL3_REF_CTRL__ACT_
FREQMHZ

100

PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ

599.994

PSU__CRF_APB__DPDMA_REF_CTRL__
ACT_FREQMHZ

599.994

PSU__CRF_APB__TOPSW_MAIN_CTRL__
ACT_FREQMHZ

499.995

PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ

99.999

PSU__CRF_APB__GTGREF0_REF_CTRL__
ACT_FREQMHZ

-1

PSU__CRF_APB__DBG_TSTMP_CTRL__
ACT_FREQMHZ

249.997

PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ

125

PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ

125

PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ

125

PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ

125

PSU__CRL_APB__GEM_TSU_REF_CTRL__
ACT_FREQMHZ

250

PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ

250

PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ

250

PSU__CRL_APB__QSPI_REF_CTRL__ACT_
FREQMHZ

300

PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ

200

PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ

200

PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ

100

PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ

100

PSU__CRL_APB__I2C0_REF_CTRL__ACT_
FREQMHZ

100

Clocking related Parameters and Divisors

(continued)

PSU__CRL_APB__I2C1_REF_CTRL__ACT_
FREQMHZ

100

PSU__CRL_APB__SPI0_REF_CTRL__ACT_
FREQMHZ

214

PSU__CRL_APB__SPI1_REF_CTRL__ACT_
FREQMHZ

214

PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ

100

PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ

100

PSU__CRL_APB__DEBUG_R5_ATCLK_
CTRL__ACT_FREQMHZ

1000

PSU__CRL_APB__CPU_R5_CTRL__ACT_
FREQMHZ

499.995

PSU__CRL_APB__OCM_MAIN_CTRL__
ACT_FREQMHZ

500

PSU__CRL_APB__IOU_SWITCH_CTRL__
ACT_FREQMHZ

249.997

PSU__CRL_APB__CSU_PLL_CTRL__ACT_
FREQMHZ

180

PSU__CRL_APB__PCAP_CTRL__ACT_
FREQMHZ

249.997

PSU__CRL_APB__LPD_LSBUS_CTRL__
ACT_FREQMHZ

99.999

PSU__CRL_APB__LPD_SWITCH_CTRL__
ACT_FREQMHZ

499.995

PSU__CRL_APB__DBG_LPD_CTRL__ACT_
FREQMHZ

249.997

PSU__CRL_APB__NAND_REF_CTRL__
ACT_FREQMHZ

100

PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ

499.995

PSU__CRL_APB__DLL_REF_CTRL__ACT_
FREQMHZ

1500

PSU__CRL_APB__AMS_REF_CTRL__ACT_
FREQMHZ

50

PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ

99.999

PSU__CRL_APB__AFI6_REF_CTRL__ACT_
FREQMHZ

500

Clocking related Parameters and Divisors

(continued)

PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ

20

PSU__CRF_APB__ACPU_CTRL__
FREQMHZ

0.000000,1500.000000

1200

PSU__CRF_APB__DBG_TRACE_CTRL__
FREQMHZ

0.000000,125.000000

125

PSU__CRF_APB__DBG_FPD_CTRL__
FREQMHZ

0.000000,250.000000

250

PSU__CRF_APB__APM_CTRL__FREQMHZ

-2,-1

1

PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ

0.000000,320.000000

320

PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ

0.000000,25.000000

25

PSU__CRF_APB__DP_STC_REF_CTRL__
FREQMHZ

0.000000,27.000000

27

PSU__CRF_APB__DDR_CTRL__FREQMHZ

100.000000,667.000000

800

PSU__CRF_APB__GPU_REF_CTRL__
FREQMHZ

0.000000,667.000000

500

PSU__CRF_APB__AFI0_REF_CTRL__
FREQMHZ

0.000000,667.000000

667

PSU__CRF_APB__AFI1_REF_CTRL__
FREQMHZ

0.000000,667.000000

667

PSU__CRF_APB__AFI2_REF_CTRL__
FREQMHZ

0.000000,667.000000

667

PSU__CRF_APB__AFI3_REF_CTRL__
FREQMHZ

0.000000,667.000000

667

PSU__CRF_APB__AFI4_REF_CTRL__
FREQMHZ

0.000000,667.000000

667

PSU__CRF_APB__AFI5_REF_CTRL__
FREQMHZ

0.000000,667.000000

667

PSU__CRF_APB__SATA_REF_CTRL__
FREQMHZ

0.000000,250.000000

250

PSU__CRF_APB__PCIE_REF_CTRL__
FREQMHZ

0.000000,250.000000

250

PSU__CRL_APB__PL0_REF_CTRL__
FREQMHZ

0.000000,400.000000

100

PSU__CRL_APB__PL1_REF_CTRL__
FREQMHZ

0.000000,400.000000

100

PSU__CRL_APB__PL2_REF_CTRL__
FREQMHZ

0.000000,400.000000

100

Clocking related Parameters and Divisors

(continued)

PSU__CRL_APB__PL3_REF_CTRL__
FREQMHZ

0.000000,400.000000

100

PSU__CRF_APB__GDMA_REF_CTRL__
FREQMHZ

0.000000,667.000000

600

PSU__CRF_APB__DPDMA_REF_CTRL__
FREQMHZ

0.000000,667.000000

600

PSU__CRF_APB__TOPSW_MAIN_CTRL__
FREQMHZ

0.000000,600.000000

533.33

PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ

0.000000,100.000000

100

PSU__CRF_APB__GTGREF0_REF_CTRL__
FREQMHZ

-2,-1

-1

PSU__CRF_APB__DBG_TSTMP_CTRL__
FREQMHZ

0.000000,250.000000

250

PSU__CRL_APB__GEM0_REF_CTRL__
FREQMHZ

0.000000,125.000000

125

PSU__CRL_APB__GEM1_REF_CTRL__
FREQMHZ

0.000000,125.000000

125

PSU__CRL_APB__GEM2_REF_CTRL__
FREQMHZ

0.000000,125.000000

125

PSU__CRL_APB__GEM3_REF_CTRL__
FREQMHZ

0.000000,125.000000

125

PSU__CRL_APB__GEM_TSU_REF_CTRL__
FREQMHZ

0.000000,250.000000

250

PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ

0.000000,250.000000

250

PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ

0.000000,250.000000

250

PSU__CRL_APB__QSPI_REF_CTRL__
FREQMHZ

0.000000,300.000000

300

PSU__CRL_APB__SDIO0_REF_CTRL__
FREQMHZ

0.000000,200.000000

200

PSU__CRL_APB__SDIO1_REF_CTRL__
FREQMHZ

0.000000,200.000000

200

PSU__CRL_APB__UART0_REF_CTRL__
FREQMHZ

0.000000,100.000000

100

PSU__CRL_APB__UART1_REF_CTRL__
FREQMHZ

0.000000,100.000000

100

PSU__CRL_APB__I2C0_REF_CTRL__
FREQMHZ

0.000000,100.000000

100

Clocking related Parameters and Divisors

(continued)

PSU__CRL_APB__I2C1_REF_CTRL__
FREQMHZ

0.000000,100.000000

100

PSU__CRL_APB__SPI0_REF_CTRL__
FREQMHZ

0.000000,200.000000

200

PSU__CRL_APB__SPI1_REF_CTRL__
FREQMHZ

0.000000,200.000000

200

PSU__CRL_APB__CAN0_REF_CTRL__
FREQMHZ

0.000000,100.000000

100

PSU__CRL_APB__CAN1_REF_CTRL__
FREQMHZ

0.000000,100.000000

100

PSU__CRL_APB__DEBUG_R5_ATCLK_
CTRL__FREQMHZ

0.000000,1000.000000

1000

PSU__CRL_APB__CPU_R5_CTRL__
FREQMHZ

0.000000,500.000000

500

PSU__CRL_APB__OCM_MAIN_CTRL__
FREQMHZ

0.000000,600.000000

500

PSU__CRL_APB__IOU_SWITCH_CTRL__
FREQMHZ

0.000000,267.000000

267

PSU__CRL_APB__CSU_PLL_CTRL__
FREQMHZ

0.000000,400.000000

180

PSU__CRL_APB__PCAP_CTRL__FREQMHZ

0.000000,250.000000

250

PSU__CRL_APB__LPD_LSBUS_CTRL__
FREQMHZ

0.000000,100.000000

100

PSU__CRL_APB__LPD_SWITCH_CTRL__
FREQMHZ

0.000000,600.000000

500

PSU__CRL_APB__DBG_LPD_CTRL__
FREQMHZ

0.000000,267.000000

250

PSU__CRL_APB__NAND_REF_CTRL__
FREQMHZ

0.000000,100.000000

100

PSU__CRL_APB__ADMA_REF_CTRL__
FREQMHZ

0.000000,600.000000

500

PSU__CRL_APB__DLL_REF_CTRL__
FREQMHZ

0.000000,1500.000000

1500

PSU__CRL_APB__AMS_REF_CTRL__
FREQMHZ

0.000000,52.000000

50

PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ

0.000000,100.000000

100

PSU__CRL_APB__AFI6_REF_CTRL__
FREQMHZ

0.000000,600.000000

500

PSU__CRL_APB__USB3_DUAL_REF_CTRL_FREQMHZ

0.000000,20.000000

20

Clocking related Parameters and Divisors

(continued)

PSU__IOU_SLCR__TTC0__FREQMHZ

0.000000,600.000000

100

PSU__IOU_SLCR__TTC1__FREQMHZ

0.000000,600.000000

100

PSU__IOU_SLCR__TTC2__FREQMHZ

0.000000,600.000000

100

PSU__IOU_SLCR__TTC3__FREQMHZ

0.000000,600.000000

100

PSU__IOU_SLCR__WDT0__FREQMHZ

0.000000,100.000000

100

PSU__FPD_SLCR__WDT1__FREQMHZ

0.000000,100.000000

100

CSU Tamper Enable

PSU__CSU__CSU_TAMPER_0__ENABLE

0,1

0

PSU__CSU__CSU_TAMPER_1__ENABLE

0,1

0

PSU__CSU__CSU_TAMPER_2__ENABLE

0,1

0

PSU__CSU__CSU_TAMPER_3__ENABLE

0,1

0

PSU__CSU__CSU_TAMPER_4__ENABLE

0,1

0

PSU__CSU__CSU_TAMPER_5__ENABLE

0,1

0

PSU__CSU__CSU_TAMPER_6__ENABLE

0,1

0

PSU__CSU__CSU_TAMPER_7__ENABLE

0,1

0

PSU__CSU__CSU_TAMPER_8__ENABLE

0,1

0

PSU__CSU__CSU_TAMPER_9__ENABLE

0,1

0

PSU__CSU__CSU_TAMPER_10__ENABLE

0,1

0

PSU__CSU__CSU_TAMPER_11__ENABLE

0,1

0

PSU__CSU__CSU_TAMPER_12__ENABLE

0,1

0

CSU Tamper Erase block RAM

PSU__CSU__CSU_TAMPER_0__ERASE_
BBRAM

0,1

0

PSU__CSU__CSU_TAMPER_1__ERASE_
BBRAM

0,1

0

PSU__CSU__CSU_TAMPER_2__ERASE_
BBRAM

0,1

0

PSU__CSU__CSU_TAMPER_3__ERASE_
BBRAM

0,1

0

PSU__CSU__CSU_TAMPER_4__ERASE_
BBRAM

0,1

0

PSU__CSU__CSU_TAMPER_5__ERASE_
BBRAM

0,1

0

PSU__CSU__CSU_TAMPER_6__ERASE_
BBRAM

0,1

0

PSU__CSU__CSU_TAMPER_7__ERASE_
BBRAM

0,1

0

PSU__CSU__CSU_TAMPER_8__ERASE_
BBRAM

0,1

0

CSU Tamper Erase block RAM

(continued)

PSU__CSU__CSU_TAMPER_9__ERASE_
BBRAM

0,1

0

PSU__CSU__CSU_TAMPER_10__ERASE_
BBRAM

0,1

0

PSU__CSU__CSU_TAMPER_11__ERASE_
BBRAM

0,1

0

PSU__CSU__CSU_TAMPER_12__ERASE_
BBRAM

0,1

0

CSU Tamper Response

PSU__CSU__CSU_TAMPER_0__RESPONSE

<Select>,SEC_LOCKDOWN_0,
SEC_LOCKDOWN_1,SYS_RESET,
SYS_INTERRUPT

<Select>

PSU__CSU__CSU_TAMPER_1__RESPONSE

<Select>,SEC_LOCKDOWN_0,
SEC_LOCKDOWN_1,SYS_RESET,
SYS_INTERRUPT

<Select>

PSU__CSU__CSU_TAMPER_2__RESPONSE

<Select>,SEC_LOCKDOWN_0,
SEC_LOCKDOWN_1,SYS_RESET,
SYS_INTERRUPT

<Select>

PSU__CSU__CSU_TAMPER_3__RESPONSE

<Select>,SEC_LOCKDOWN_0,
SEC_LOCKDOWN_1,SYS_RESET,
SYS_INTERRUPT

<Select>

PSU__CSU__CSU_TAMPER_4__RESPONSE

<Select>,SEC_LOCKDOWN_0,
SEC_LOCKDOWN_1,SYS_RESET,
SYS_INTERRUPT

<Select>

PSU__CSU__CSU_TAMPER_5__RESPONSE

<Select>,SEC_LOCKDOWN_0,
SEC_LOCKDOWN_1,SYS_RESET,
SYS_INTERRUPT

<Select>

PSU__CSU__CSU_TAMPER_6__RESPONSE

<Select>,SEC_LOCKDOWN_0,
SEC_LOCKDOWN_1,SYS_RESET,
SYS_INTERRUPT

<Select>

PSU__CSU__CSU_TAMPER_7__RESPONSE

<Select>,SEC_LOCKDOWN_0,
SEC_LOCKDOWN_1,SYS_RESET,
SYS_INTERRUPT

<Select>

CSU Tamper Response

(continued)

PSU__CSU__CSU_TAMPER_8__RESPONSE

<Select>,SEC_LOCKDOWN_0,
SEC_LOCKDOWN_1,SYS_RESET,
SYS_INTERRUPT

<Select>

PSU__CSU__CSU_TAMPER_9__RESPONSE

<Select>,SEC_LOCKDOWN_0,
SEC_LOCKDOWN_1,SYS_RESET,
SYS_INTERRUPT

<Select>

PSU__CSU__CSU_TAMPER_10__
RESPONSE

<Select>,SEC_LOCKDOWN_0,
SEC_LOCKDOWN_1,SYS_RESET,
SYS_INTERRUPT

<Select>

PSU__CSU__CSU_TAMPER_11__
RESPONSE

<Select>,SEC_LOCKDOWN_0,
SEC_LOCKDOWN_1,SYS_RESET,
SYS_INTERRUPT

<Select>

PSU__CSU__CSU_TAMPER_12__
RESPONSE

<Select>,SEC_LOCKDOWN_0,
SEC_LOCKDOWN_1,SYS_RESET,
SYS_INTERRUPT

<Select>

PSU__GEN_IPI_0__MASTER

NONE,APU,RPU0,RPU1,
S_AXI_HP1_FPD,S_AXI_HP2_FPD,
S_AXI_HP3_FPD,S_AXI_LPD, S_AXI_HP0_FPD, S_AXI_HPC0_FPD,S_AXI_HPC1_FPD, S_AXI_ACP_FPD

APU

PSU__GEN_IPI_1__MASTER

NONE,APU,RPU0,RPU1,
S_AXI_HP1_FPD,S_AXI_HP2_FPD,
S_AXI_HP3_FPD,S_AXI_LPD, S_AXI_HP0_FPD, S_AXI_HPC0_FPD,S_AXI_HPC1_FPD, S_AXI_ACP_FPD

RPU0

PSU__GEN_IPI_2__MASTER

NONE,APU,RPU0,RPU1,
S_AXI_HP1_FPD,S_AXI_HP2_FPD,
S_AXI_HP3_FPD,S_AXI_LPD, S_AXI_HP0_FPD, S_AXI_HPC0_FPD,S_AXI_HPC1_FPD, S_AXI_ACP_FPD

RPU1

PSU__GEN_IPI_3__MASTER

NONE,PMU

PMU

IPI Master

PSU__GEN_IPI_4__MASTER

NONE,PMU

PMU

PSU__GEN_IPI_5__MASTER

NONE,PMU

PMU

PSU__GEN_IPI_6__MASTER

NONE,PMU

PMU

PSU__GEN_IPI_7__MASTER

NONE,APU,RPU0,RPU1,
S_AXI_HP1_FPD,S_AXI_HP2_FPD,
S_AXI_HP3_FPD,S_AXI_LPD, S_AXI_HP0_FPD, S_AXI_HPC0_FPD,S_AXI_HPC1_FPD, S_AXI_ACP_FPD

NONE

PSU__GEN_IPI_8__MASTER

NONE,APU,RPU0,RPU1,
S_AXI_HP1_FPD,S_AXI_HP2_FPD,
S_AXI_HP3_FPD,S_AXI_LPD, S_AXI_HP0_FPD, S_AXI_HPC0_FPD,S_AXI_HPC1_FPD, S_AXI_ACP_FPD

NONE

PSU__GEN_IPI_9__MASTER

NONE,APU,RPU0,RPU1,
S_AXI_HP1_FPD,S_AXI_HP2_FPD,
S_AXI_HP3_FPD,S_AXI_LPD, S_AXI_HP0_FPD, S_AXI_HPC0_FPD,S_AXI_HPC1_FPD, S_AXI_ACP_FPD

NONE

IPI Master

(Continued)

PSU__GEN_IPI_10__MASTER

NONE,APU,RPU0,RPU1,
S_AXI_HP1_FPD,S_AXI_HP2_FPD,
S_AXI_HP3_FPD,S_AXI_LPD, S_AXI_HP0_FPD, S_AXI_HPC0_FPD,S_AXI_HPC1_FPD, S_AXI_ACP_FPD

NONE

PSU__NUM_FABRIC_RESETS

0,1,2,3,4

1

PSU__GPIO_EMIO__WIDTH

NA

[94:0]

PSU__REPORT__DBGLOG

0,1

0

Notes:

1. Reserve, Wireless controller, Satellite communication controller, Data acquisition and signal processing controllers,
Intelligent I/O controllers, Docking stations, Device was built before Class Code definitions were finalized,
Memory controller, Simple communication controller, Serial bus controllers, Encryption/Decryption controller,
Display controller, Multimedia device, Input devices, Mass storage controller, Processors,
Device does not fit in any defined classes, Bridge device, Network controller, Base system peripherals, Multimedia device

2. ADMA is also referenced as LPD_DMA throughout this guide. These two terms are synonymous.

3. GDMA is also referenced as FPD_DMA throughout this guide. These two terms are synonymous.

4. PSU__PMU__EMIO_GPI__ENABLE and PSU__PMU__EMIO_GPO__ENABLE belongs to PMU processor local bank GPI3 and GPO3. While GPI3 and GPO3 are reserved for communication with the PL, GPI3 monitors the GPIs from the PL. GPO3 is dedicated to the GPOs to the PL.

5. PSU__PMU__GPI0__ENABLE to PSU__PMU__GPI5__ENABLE signals belong to PMU processor local bank GPI0 (only accessible by the PMU processor) and GPI0 is reserved for the dedicated PMU processor subsystem features. These are general purpose wakes from MIO. MIO[26] -> GPI1[10], MIO[27] -> GPI1[11] ... MIO[31] -> GPI1[15].

6. PSU__PMU__GPO0__ENABLE to PSU__PMU__GPO5__ENABLE signals belong to PMU processor local bank GPO1 (only accessible by the PMU processor) and GPO1 is reserved for the dedicated PMU processor subsystem features. GPO1 is dedicated to the GPOs assigned to the MIO for signaling and power-supply management (GPOs to MIO). Use the following guidelines to signal the powering up of power rails:

GPO1[0] = 1: Signal to turn on a basic digital switch for the FET for VCC_PSINTFP .

GPO1[1] = 1: Signal to turn on the FET for VCCINT .

SDWT1 is also referred as FPD SWDT or FPD_SWDT as this is in FPD domain.

SDWT0 is also referred as LPD SWDT or LPD_SWDT as this is in LPD domain.

7. The PSU__NUM_FABRIC_RESETS parameter will enable the PL fabric reset signals (pl_resetn{0:3}) as described in Fabric Reset Enable .

8. The default values of Clocking parameters (FBDIV, SRCSEL, DIVISOR0, DIVISOR1, etc.) mentioned in this table are part specific and depending on the speed grades. You need to open PCW and cross check for the corresponding values for these parameters based on their requirements.

Table C-2: PSU__PROTECTION__MASTERS Default Values

Default Values

USB1:NonSecure;0

USB0:NonSecure;0

S_AXI_LPD:NA;0

S_AXI_HPC1_FPD:NA;0

S_AXI_HPC0_FPD:NA;0

S_AXI_HP3_FPD:NA;0

S_AXI_HP2_FPD:NA;0

S_AXI_HP1_FPD:NA;0

S_AXI_HP0_FPD:NA;0

S_AXI_ACP:NA;0

S_AXI_ACE:NA;0

SD1:Secure;0

SD0:Secure;0

SATA1:NonSecure;0

SATA0:NonSecure;0

RPU1:Secure;1

RPU0:Secure;1

QSPI:Secure;0

PMU:NA;1

PCIe:NonSecure;0

NAND:Secure;0

LDMA:NA;1

GPU:Secure;1

GEM3:Secure;0

GEM2:Secure;0

GEM1:Secure;0

GEM0:Secure;0

FDMA:NA;1

DP:NonSecure;0

DAP:NA;1’

Coresight:NA;1

CSU:NA;1

APU:NA;1

Table C-3: PSU__PROTECTION__SLAVES

Default Values

LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0

LPD;USB3_1;FF9E0000;FF9EFFFF;0

LPD;USB3_0_XHCI;FE200000;FE2FFFFF;0

LPD;USB3_0;FF9D0000;FF9DFFFF;0

LPD;UART1;FF010000;FF01FFFF;0

LPD;UART0;FF000000;FF00FFFF;0

LPD;TTC3;FF140000;FF14FFFF;0

LPD;TTC2;FF130000;FF13FFFF;0

LPD;TTC1;FF120000;FF12FFFF;0

LPD;TTC0;FF110000;FF11FFFF;0

FPD;SWDT1;FD4D0000;FD4DFFFF;0

LPD;SWDT0;FF150000;FF15FFFF;0

LPD;SPI1;FF050000;FF05FFFF;0

LPD;SPI0;FF040000;FF04FFFF;0

FPD;SMMU_REG;FD5F0000;FD5FFFFF;1

FPD;SMMU;FD800000;FDFFFFFF;1

FPD;SIOU;FD3D0000;FD3DFFFF;1

FPD;SERDES;FD400000;FD47FFFF;1

LPD;SD1;FF170000;FF17FFFF;0

LPD;SD0;FF160000;FF16FFFF;0

FPD;SATA;FD0C0000;FD0CFFFF;0

LPD;RTC;FFA60000;FFA6FFFF;1

LPD;RSA_CORE;FFCE0000;FFCEFFFF;1

LPD;RPU;FF9A0000;FF9AFFFF;1

FPD;RCPU_GIC;F9000000;F900FFFF;1

LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1

LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1

LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1

LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1

LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1

LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1

LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1

LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1

LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1

LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1

LPD;QSPI;FF0F0000;FF0FFFFF;0

LPD;PMU_RAM;FFDC0000;FFDDFFFF;1

LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1

FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0

FPD;PCIE_LOW;E0000000;EFFFFFFF;0

FPD;PCIE_HIGH;600000000;7FFFFFFFF;0

FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0

FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0

LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1

LPD;OCM_SLCR;FF960000;FF96FFFF;1

OCM;OCM;FFFC0000;FFFFFFFF;1

LPD;NAND;FF100000;FF10FFFF;0

LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1

LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1

LPD;LPD_XPPU;FF980000;FF98FFFF;1

LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1

LPD;LPD_SLCR;FF410000;FF4AFFFF;1

LPD;LPD_GPV;FE100000;FE1FFFFF;1

LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1

LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1

LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1

LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1

LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1

LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1

LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1

LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1

LPD;IPI_CTRL;FF380000;FF3FFFFF;1

LPD;IOU_SLCR;FF180000;FF23FFFF;1

LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1

LPD;IOU_SCNTRS;FF260000;FF26FFFF;1

LPD;IOU_SCNTR;FF250000;FF25FFFF;1

LPD;IOU_GPV;FE000000;FE0FFFFF;1

LPD;I2C1;FF030000;FF03FFFF;0

LPD;I2C0;FF020000;FF02FFFF;0

FPD;GPU;FD4B0000;FD4BFFFF;1

LPD;GPIO;FF0A0000;FF0AFFFF;1

LPD;GEM3;FF0E0000;FF0EFFFF;0

LPD;GEM2;FF0D0000;FF0DFFFF;0

LPD;GEM1;FF0C0000;FF0CFFFF;0

LPD;GEM0;FF0B0000;FF0BFFFF;0

FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1

FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1

FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1

FPD;FPD_SLCR;FD610000;FD68FFFF;1

FPD;FPD_GPV;FD700000;FD7FFFFF;1

FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1

FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1

FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1

FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1

FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1

FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1

FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1

FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1

LPD;EFUSE;FFCC0000;FFCCFFFF;1

FPD;Display Port;FD4A0000;FD4AFFFF;0

FPD;DPDMA;FD4C0000;FD4CFFFF;1

FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1

FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1

FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1

FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1

FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1

FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1

FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1

FPD;DDR_PHY;FD080000;FD08FFFF;1

DDR;DDR_LOW;0;7FFFFFFF;1

DDR;DDR_HIGH;800000000;800000000;0

FPD;DDDR_CTRL;FD070000;FD070FFF;1

LPD;Coresight;FE800000;FEFFFFFF;1

LPD;CSU_DMA;FFC80000;FFC9FFFF;1

LPD;CSU;FFCA0000;FFCAFFFF;0

LPD;CRL_APB;FF5E0000;FF85FFFF;1

FPD;CRF_APB;FD1A0000;FD2DFFFF;1

FPD;CCI_REG;FD5E0000;FD5EFFFF;1

FPD;CCI_GPV;FD6E0000;FD6EFFFF;1

LPD;CAN1;FF070000;FF07FFFF;0

LPD;CAN0;FF060000;FF06FFFF;0

FPD;APU;FD5C0000;FD5CFFFF;1

LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1

LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1

FPD;APM_5;FD490000;FD49FFFF;1

FPD;APM_0;FD0B0000;FD0BFFFF;1

LPD;APM2;FFA10000;FFA1FFFF;1

LPD;APM1;FFA00000;FFA0FFFF;1

LPD;AMS;FFA50000;FFA5FFFF;1

FPD;AFI_5;FD3B0000;FD3BFFFF;1

FPD;AFI_4;FD3A0000;FD3AFFFF;1

FPD;AFI_3;FD390000;FD39FFFF;1

FPD;AFI_2;FD380000;FD38FFFF;1

FPD;AFI_1;FD370000;FD37FFFF;1

FPD;AFI_0;FD360000;FD36FFFF;1

LPD;AFIFM6;FF9B0000;FF9BFFFF;1

FPD;ACPU_GIC;F9000000;F907FFFF;1