MIPI D-PHY LogiCORE IP Product Guide (PG202) - 4.3 English

Document ID: PG202
Release Date: 2022-04-20
Version: 4.3 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Feature Summary
Applications
Unsupported Features
Licensing and Ordering
Product Specification
Standards
MIPI D-PHY TX (Master) Core Architecture
MIPI D-PHY RX (Slave) Core Architecture
MIPI D-PHY Splitter Bridge Mode
Performance and Resource Use
Port Descriptions
PPI Signals
Clocking and Reset Signals
I/O Interface Signals
AXI4-Lite Interface Signals
7 Series FPGA Families Calibration Logic Signals
Active Lane Support Signals
Register Space
Endianness Details
CONTROL Registers
IDELAY_TAP_VALUE for Lanes 1 to 4
INIT Register
HS_TIMEOUT Register
ESC_TIMEOUT Register
CL_STATUS Register
DL_STATUS Register
HS_SETTLE Register
IDELAY_TAP_VALUE for Lanes 5 to 8
Designing with the Core
General Design Guidelines
Use the Example Design
Know the Degree of Difficulty
Registering Signals
Recognize Timing Critical Signals
Make Only Allowed Modifications
I/O Placement
Shared Logic
Shared Logic in Core
Shared Logic in Example Design
Case 1: UltraScale+ Device MIPI D-PHY TX Core
Case 2: UltraScale+ Device MIPI D-PHY RX Core
Case 3: 7 Series FPGAs MIPI D-PHY TX Core
I/O Planning for UltraScale+ Devices
I/O Planning for Versal Devices
Clocking
Resets
Resetting the MIPI D-PHY TX and RX Core
Resetting TX-Only Designs
Resetting RX-Only Designs
Protocol Description
Initialization
High Speed Transfer
High Frequency Clock Transmission
Escape Mode
Remote Triggers
Low Power Data Transmission
Ultra-Low Power State
Interfaces
PPI Interface
Example 1: High-Speed Transmit from D-PHY TX (Master) Side
Example 2: Low-Power Data Transfer from D-PHY TX (Master) Side
Example 3: Trigger Command Transmission from D-PHY TX (Master) Side
Example 4: D-PHY TX (Master) Data Lane ULPS Operation
Example 5: D-PHY TX (Master) Clock Lane ULPS Operation
Example 6: High-Speed Receive at D-PHY RX (Slave) Side
Example 7: High-Speed Receive with Synchronization Error at D-PHY RX (Slave) Side
Example 8: High-Speed Mode Data Receive with Loss of Synchronization at D-PHY RX (Slave) Side
Example 9: Low-Power Receive at D-PHY RX (Slave) Side
Example 10: Low-Power Data Receive with Synchronization Error at D-PHY RX (Slave) Side
Example 11: ULPS Operation at D-PHY RX (Slave) Data Lane
Example 12: ULPS Operation at D-PHY RX (Slave) Clock Lane
Example 13: RX Data Lane Initialization Using forcerxmode
AXI4-Lite Interface
Design Flow Steps
Customizing and Generating the Core
Core Configuration Tab
Shared Logic Tab
Pin Assignment Tab
User Parameters
Output Generation
Constraining the Core
Simulation
Synthesis and Implementation
Example Design
Overview
Simulating the Example Design
Test Bench
Verification, Compliance, and Interoperability
Hardware Validation
Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Master Answer Record for the Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Simulation Debug
Hardware Debug
General Checks
D-PHY Protocol Checks
Lane Initialization
HS Clock Transfer
HS Data Transfer
AXI4-Lite Interface Debug
Pin and Bank Rules
Pin and Bank Rules for Versal ACAP
Pin Rules for Zynq UltraScale+ MPSoC Devices
D-PHY RX Pin Rules
Strobe Propagation for D-PHY RX
D-PHY TX Pin Rules
Pin Rules for 7 series FPGAs
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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