7 Series FPGA Families Calibration Logic Signals - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)
Document ID
PG202
Release Date
2023-05-16
Version
4.3 English

D-PHY RX IP includes calibration logic for 7 series FPGA families. The following table lists ports associated with the calibration logic.

Table 1. 7 Series FPGA Families Calibration Logic Signals
Signal Direction Clock Domain Description
dlyctrl_rdy_out Output N/A Ready signal output from IDEALYCTRL, stating delay values are adjusted as per vtc changes.
dlyctrl_rdy_in Input N/A Ready signal input to IDELAYCTRL See 'Include IDELAYCTRL in Core' in the Core Configuration Tab section.