AXI4-Lite Interface - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

Document ID
PG202
Release Date
2023-05-16
Version
4.3 English
The register interface uses an AXI4-Lite interface, which was selected because of its simplicity. The following figures show typical AXI4-Lite write and read transaction timings.
Figure 1. AXI4-Lite Write Timing Diagram
Figure 2. AXI4-Lite Read Timing Diagram