Clocking - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)
Document ID
PG202
Release Date
2023-05-16
Version
4.3 English
The MIPI D-PHY Controller requires a 200 MHz free running clock (core_clk). This clock is used as input to the Mixed-Mode Clock Manager (MMCM), and the required clocks are generated based on IP configurations.
Important: core_clk should be either coming from the on-board oscillator or the single MMCM or the PLL from target FPGA device. core_clk should not be generated from the cascaded MMCM blocks.

The following figures show the MIPI D-PHY Controller clock diagrams for supported families. The MIPI D-PHY TX core takes core_clk as an input and generates the necessary clocks from the MMCM. The clkoutphy signal from the PLL is used in the BITSLICE_CONTROL of the PHY block in native mode.

Figure 1. MIPI D-PHY Core TX Clocking for Versal Adaptive SoC
Figure 2. MIPI D-PHY Core TX Clocking for UltraScale+ Families
Figure 3. MIPI D-PHY Core RX Clocking for UltraScale+ and Versal Adaptive SoC where Line Rates ≤ 1500 Mbps
Note: For line rates less than or equal to 1500 Mbps, the frequency value is 1500. When line rates are greater than 1500 Mbps, the frequency value is equal to the line rate.
Figure 4. MIPI D-PHY Core RX Clocking for UltraScale+ and Versal Adaptive SoC where Line Rates >1500 Mbps
Note: For line rates less than or equal to 1500 Mbps, the frequency value is 1500. When line rates are greater than 1500 Mbps, the frequency value is equal to the line rate.

The following figures show the MIPI D-PHY Controller clock diagrams for 7 series FPGA families. The MIPI D-PHY Controller takes core_clk as an input and generates the necessary clocks from the MMCM for D-PHY TX IP. MMCM is not used in the D-PHY RX IP when the line rate is less than or equal to 1500 Mbps; for line rates greater than 1500 Mbps, MMCM is used.

Figure 5. MIPI D-PHY Core TX Clocking for 7 Series FPGA Families
Figure 6. MIPI D-PHY Core RX Clocking for 7 Series FPGA Families

The following table provides details about the core clocks.

Table 1. MIPI D-PHY Clocking Details
Clock Frequency IP Configuration Notes
core_clk 200.000 MHz All Used for control logic and input to MMCM.
txbyteclkhs 1 10.000–187.500 MHz Derived from the line rate divided by 8 MIPI D-PHY TX core Shared Logic in Core Input to PHY and used to transmit high-speed data. This clock is generated from oserdes_clk90_out as source for 7 series FPGAs.
xiphy_byteclk_out 1 75.000–187.500 MHz Line rate divided by ratio 2 MIPI D-PHY TX core Shared Logic in Core Line rate < 600 Mbps This output clock is used in high-speed data transfer. For use case details, see Case 4: UltraScale+ Device MIPI D-PHY TX Core (Line rates below 600 Mbps). This clock is not available for 7 series FPGA families.
clkoutphy_out 1 Line rate Shared Logic in Core PHY serial clock. This clock is not available for the 7 series FPGA families.
txclkesc_out 10.000–20.000 MHz MIPI D-PHY TX core Shared Logic in Core Clock used for Escape mode operations
txbyteclkhs_in 1 10.000–187.500 MHz Derived from the line rate divided by 8. MIPI D-PHY TX core Shared Logic in Example Design Input to PHY and used to transmit high-speed data. This clock should be generated from oserdes_clk90_in as source for the 7 series FPGA families.
xiphy_byteclk_in 1 75.000–187.500 MHz Line rate divided by ratio 2 MIPI D-PHY TX core Shared Logic in Example Design Line rates < 600 Mbps. This input clock is used in high-speed data transfer. For use case details see Case 4: UltraScale+ Device MIPI D-PHY TX Core (Line rates below 600 Mbps). This clock is not available for 7 series FPGA families.
clkoutphy_in 1 Line rate Shared Logic in Example Design PHY serial clock. This clock is not available for the 7 series FPGA families.
txclkesc_in 10.000–20.000 MHz MIPI D-PHY TX core Shared Logic in Example Design Clock used for Escape mode operations
rxbyteclkhs 10.000–187.500 MHz Derived from the line rate divided by 8. MIPI D-PHY RX core Clock received on RX clock lane and used for high-speed data reception
oserdes_clk_out line rate/2 7 series FPGA families and Shared Logic is in the core and D-PHY TX configuration Used to connect the CLK pin of TX clock lane OSERDES
oserdes_clk90_out line rate/2 7 series FPGA families and Shared Logic is in the core and D-PHY TX configuration Used to connect the CLK pin of TX data lane OSERDES. It has 90 degree phase shift relationship with oserdes_clk_out
oserdes_clkdiv_out line rate/8 7 series FPGA families and Shared Logic is in the core and D-PHY TX configuration Used to connect the CLKDIV pin of TX clock lane OSERDES and generated from oserdes_clk_out as source
oserdes_clk_in line rate/2 7 series FPGA families and Shared Logic is in the Example Design and D-PHY TX configuration Used to connect the CLK pin of TX clock lane OSERDES
oserdes_clk90_in line rate/2 7 series FPGA families and Shared Logic is in the Example Design and D-PHY TX configuration Used to connect the CLK pin of TX data lane OSERDES and should have 90 degree phase shift with oserdes_clk_in
oserdes_clkdiv_in line rate/8 7 series FPGA families and Shared Logic is in the Example Design and D-PHY TX configuration Used to connect the CLKDIV pin of TX clock lane OSERDES and should be generated from oserdes_clk_in as source
cl_tst_clk_in line rate/2 7 series FPGA families D-PHY TX configuration and Shared Logic is in the Example Design and Infer OBUFTDS option is selected Used for TX clock lane IO buffer tristate signal synchronization
dl_tst_clk_in line rate/2 7 series FPGA families D-PHY TX configuration and Shared Logic is in the Example Design and Infer OBUFTDS option is selected Used for TX data lane IO buffer tristate signal synchronization
cl_tst_clk_out line rate/2 7 series FPGA families D-PHY TX configuration and Shared Logic is in the core and Infer OBUFTDS option is selected Used for TX clock lane IO buffer tristate signal synchronization
dl_tst_clk_in line rate/2 7 series FPGA families D-PHY TX configuration and Shared Logic is in the core and Infer OBUFTDS option is selected Used for TX data lane IO buffer tristate signal synchronization
  1. The txbyteclkhs and xiphy_byteclk clocks should be generated from same clock source or PLL.
  2. Ratios for various line rate range are as follows:
    • 4 for 300 to 599 Mbps.
    • 2 for 150 to 299 Mbps.
    • 1 for 80 to 149 Mbps.

For example, the xiphy_byteclk frequency is 125.000 MHz for 500 Mbps line rate.
Important: All the input clocks supplied to the MIPI D-PHY core should have ±100 PPM difference and violating this results in either data corruption or data duplication.