Clocking and Reset Signals

Clocking and Reset Signals - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

Document ID

PG202

Release Date

2023-05-16

Version

4.3 English

Included in the example design sources are circuits for clock and reset management. The following table shows the ports on the core that are associated with system clock and reset.

Table 1. Clocking and Reset Signals
Signal	Direction	Clock Domain	Description
core_clk	Input	N/A	A stable core clock used for control logic.
core_rst	Input	core_clk	An active-High reset signal.
system_rst_out	Output	core_clk	An active-High system reset output to be used by the example design level logic. This port is available when Shared Logic is in the Core is selected.
mmcm_lock_out	Output	Async	MMCM lock indication. This port is not available when shared logic in the core is selected in D-PHY TX Configuration.
pll_lock_out	Output	Async	PLL lock indication. This port is available when Shared Logic is in the Core is selected. This port is available for UltraScale+ families.
system_rst_in	Input	core_clk	System level reset. This port is available when Shared Logic is in Example Design is selected in D-PHY TX configuration.
pll_lock_in	Input	Async	PLL lock indication, This port is available when Shared Logic is in Example Design is selected. This port is available for UltraScale+ families.
ssc_byteclkhs_in	Input	N/A	SSC enabled clock input when the example design is in the core and the line rate is greater than 2500 Mbps.
spltdl<>_rxbyteclkhs	Input	N/A	Clock for input splitter interface. Note: This pin is only available when splitter bridge mode is enabled.
init_done	Output	core_clk	An active-High signal which indicates lane initialization is done.
ext_mmcm_clk_in	Input	External mmcm clock input.	When the External MMCM option is selected. Only applicable for SLAVE MODE and for UltraScale+ devices with Line rates > 1500.
ext_mmcm_lock_in	Input	External mmcm lock input.	When the External MMCM option is selected Only applicable for SLAVE MODE and for UltraScale+ devices with Line rates > 1500.
ext_mmcm_clk_out	Output	mmcm clock output.	When the Internal MMCM option is selected. Only applicable for SLAVE MODE and for UltraScale+ devices with Line rates > 1500.
ext_mmcm_lock_out	Output	mmcm lock output.	When the Internal MMCM option is selected. Only applicable for SLAVE MODE and for UltraScale+ devices with Line rates > 1500.