ESC_TIMEOUT Register - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

Document ID
PG202
Release Date
2023-05-16
Version
4.3 English
The ESC_TIMEOUT register (0x14 offset) is used for the watchdog timer in escape mode. The following table shows the ESC_TIMEOUT register bit description.
Table 1. ESC_TIMEOUT Register Bit Description
Bits Name Access Default Value Description
31:0 ESC_TIMEOUT R/W 25,600 ns Escape timeout period in ns. Timeout occurs for the data lanes in escape mode.