Example 1: High-Speed Transmit from D-PHY TX (Master) Side - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)
Document ID
PG202
Release Date
2023-05-16
Version
4.3 English
This section describes a high-speed transmission by the D-PHY TX (Master) IP.
  1. While txrequesths is Low, the lane module ignores the value of txdatahs[7:0]. To begin transmission, the protocol drives the txdatahs signal with the first byte of data and asserts the txrequesths signal.
  2. This data byte is accepted by the D-PHY on the first rising edge of txbyteclkhs with txreadyhs also asserted. Now, the protocol logic drives the next data byte onto txdatahs. After every rising clock cycle with txreadyhs active, the protocol supplies a new valid data byte or ends the transmission.
  3. After the last data byte has been transferred to the lane module, txrequesths is driven Low to cause the lane module to stop the transmission and enter Stop state.
  4. The txreadyhs signal is driven Low after txrequesths goes Low.
The minimum number of bytes transmitted can be as small as one.
Note: The txrequesths signal of the TX clock lane must be asserted to start the high-speed data transfer.
The following figure shows the high-speed transmission by the D-PHY TX (Master) IP.
Figure 1. High-Speed Mode Data Transfer from D-PHY TX (Master)

The start-up time can be calculated using.

2*LPX_TIME + HS_PREPARE_TIME + HS_ZERO_TIME + CDC_DELAY.

Where HS_PREPARE and HS_ZERO are D-PHY protocol timing parameters and maximum values used in the IP. You cannot control theHS_PREPARE and HS_ZERO values as they are automatically calculated based on the line rate. You can configure LPX using the AMD Vivado™ IP Catalog. CDC_DELAY will be 30 ns + 2 txbyteclkhs.