This section describes a high-speed reception at the slave side PPI. This behavior is shown in the following figure.
The rxactivehs signal indicates that a receive operation is occurring. A
normal reception starts with a pulse on rxsynchs followed by valid receive
data on subsequent cycles of rxbyteclkhs. Note that the protocol is prepared
to receive all of the data. There is no method for the receiving protocol to pause or slow
data reception.
Because end-of-transmission (EoT) processing is not performed in the PHY, one
or more additional bytes are presented after the last valid data byte. The first of these
additional bytes, shown as byte “C” in the following figure, is either all 1s or all 0s.
Subsequent bytes might or might not be present and can have any value. The
rxactivehs and rxvalidhs signals
transition Low simultaneously sometime after byte “C” is received. After these signals have
transitioned Low, they remain Low until the next high-speed data reception begins.Figure 1. High-Speed Mode Data Receive at the D-PHY RX (Slave)
Note: D-PHY RX data lanes operate
independently and the received high-speed data, from the serial lines, is passed to the
higher layers through PPI. MIPI D-PHY RX IP does not perform any byte alignment or
inter-lane skew between RX data lanes. It is the responsibility of the higher layer protocol
cores. MIPI CSI-2 Receiver Subsystem compensates up to two
rxbyteclkhs clock cycles between RX data lanes PPI
High-Speed data.