The MIPI D-PHY Controller can be configured as a Master (TX) or Slave (RX). It supports high-speed data transfer up to 3200 Mbps, and control data can be transferred using Low-Power Data Transfer mode at 10 Mbps. The PPI interface allows a seamless interface to DSI and/or CSI IP cores. Using the MIPI D-PHY core AMD Vivado™ Integrated Design Environment (IDE)-based I/O planner, you can customize the data lane(s) selection by selecting the I/O bank followed by the clock lane. Optionally, the MIPI D-PHY core provides an AXI4-Lite interface to update the protocol timer values and retrieve the core status for debugging purposes.