The HS_SETTLE register (0x30 offset,
0x48 to 0x60 offset) provides control to update the HS_SETTLE timing parameter for RX data
lanes. The following table provides the HS_SETTLE register bit description.
| Bits | Name | Access | Default Value | Description |
|---|---|---|---|---|
| 31:9 | Reserved | RO | 0 | Reserved |
| 8:0 | HS_SETTLE_NS | R/W | 135 + 10 UI | HS_SETTLE timing parameter (ns). This value will be
applied for all data lanes and will only be applicable for D-PHY RX configuration.
Note: UI is unit interval.
|