The example design includes circuits
for PHY management and D-PHY compatible I/O connectivity. The following table shows the core
ports that are associated with the I/O interface.
Signal | Direction | Clock Domain | Description |
---|---|---|---|
clk_txp | Output | N/A | Positive differential serial data output pin for clock lane. Available only for UltraScale+, Versal Adaptive SoC. |
clk_txn | Output | N/A | Negative differential serial data output pin for clock lane. Available only for UltraScale+, Versal Adaptive SoC. |
data_txp[<n-1>:0] 1 | Output | N/A | Positive differential serial data output pin for data lane(s). Available only for UltraScale+, Versal Adaptive SoC. |
data_txn[<n-1>:0] 1 | Output | N/A | Negative differential serial data output pin for data lane(s). Available only for UltraScale+, Versal Adaptive SoC. |
clk_hs_txp | Output | N/A | High-Speed positive differential serial data output pin for clock lane. Available only for 7 series FPGA families. |
clk_hs_txn | Output | N/A | High-Speed negative differential serial data output pin for clock lane. Available only for 7 series FPGA families. |
clk_lp_txp | Output | N/A | Low-Power positive serial data output pin for clock lane. Available only for 7 series FPGA families. |
clk_lp_txn | Output | N/A | Low-Power negative serial data output pin for clock lane. Available only for 7 series FPGA families. |
data_hs_txp[<n-1>:0] 1 | Output | N/A | High-Speed positive differential serial data output pin for data lane(s). Available only for 7 series FPGA families. |
data_hs_txn[<n-1>:0] 1 | Output | N/A | High-Speed negative differential serial data output pin for data lane(s). Available only for 7 series FPGA families. |
data_lp_txp[<n-1>:0] 1 | Output | N/A | Low-Power positive serial data output pin for data lane(s). Available only for 7 series FPGA families. |
data_lp_txn[<n-1>:0] 1 | Output | N/A | Low-Power negative serial data output pin for data lane(s). Available only for 7 series FPGA families. |
|
Signal | Direction | Clock Domain | Description |
---|---|---|---|
clk_rxp | Input | N/A | Positive differential serial data input pin for clock lane. Available only for UltraScale+, Versal Adaptive SoC. |
clk_rxn | Input | N/A | Negative differential serial data input pin for clock lane. Available only for UltraScale+, Versal Adaptive SoC. |
data_rxp[<n-1>:0] 1 | Input | N/A | Positive differential serial data input pin for data lane(s). Available only for UltraScale+, Versal Adaptive SoC. |
data_rxn[<n-1>:0] 1 | Input | N/A | Negative differential serial data input pin for data lane(s). Available only for UltraScale+, Versal Adaptive SoC. |
bg<x>_pin<y>_nc | Input | N/A | Inferred bitslice ports. The core infers bitslice0 of a nibble
for strobe propagation within the byte group; <x> indicates byte group
(0,1,2,3); <y> indicates bitslice0 position (0 for the lower nibble, 6 for the
upper nibble.)
Note: Pins are available only for UltraScale+ families.
|
clk_hs_rxp | Input | N/A | High-Speed positive differential serial data input pin for clock lane. Available only for 7 series FPGA families. |
clk_hs_rxn | Input | N/A | High-Speed negative differential serial data input pin for clock lane. Available only for 7 series FPGA families. |
clk_lp_rxp | Input | N/A | Low-Power positive serial data input pin for clock lane. Available only for 7 series FPGA families. |
clk_lp_rxn | Input | N/A | Low-Power negative serial data input pin for clock lane. Available only for 7 series FPGA families. |
data_hs_rxp[<n-1>:0] 1 | Input | N/A | High-Speed positive differential serial data input pin for data lane(s). Available only for 7 series FPGA families. |
data_hs_rxn[<n-1>:0] 1 | Input | N/A | High-Speed negative differential serial data input pin for data lane(s). Available only for 7 series FPGA families. |
data_lp_rxp[<n-1>:0] 1 | Input | N/A | Low-Power positive serial data input pin for data lane(s). Available only for 7 series FPGA families. |
data_lp_rxn[<n-1>:0] 1 | Input | N/A | Low-Power negative serial data input pin for data lane(s). Available only for 7 series FPGA families. |
|