The MIPI D-PHY protocol supports the MIPI_DPHY_DCI I/O standard, and this I/O standard is supported only in the HP I/O bank in AMD UltraScale+™ and AMD Zynq™ UltraScale+™ MPSoC devices and in the XPIO bank in AMD Versal™ Adaptive SoCs. It is recommended that you use consecutive bit slices for data lanes starting from the clock lane BITSLICE. All I/O placements should be restricted to the same I/O bank.