The MIPI D-PHY Controller provides an I/O planner feature for I/O selection. You can select any I/O for the clock and data lanes in the TX core configuration for the selected HP I/O bank.
For the RX core configuration, dedicated byte clocks (DBC) or quad byte clocks (QBC) are listed for the clock lane for the selected HP I/O bank. For the QBC clock lane all of the I/O pins are listed for data lane I/O selection but for the DBC clock lane only byte group I/O pins are listed for data lane I/O selection in the RX core configuration.
Eight D-PHY IP cores can be implemented per IO bank due to BITSLICE and
BITSLICE_CONTROL instances in UltraScale+ devices.
Important: If the RX data lane
I/O pins are selected non-contiguously then an additional one, two, or three I/O pins
(RX_BITSLICE) are automatically used for clock/Strobe propagation. Therefore, it is
recommended that you select adjacent I/O pins for the RX configuration to make efficient use
of the I/O. The propagation of strobes to the RX data pins follows the inter-byte and
inter-nibble clocking rules given in the
UltraScale
Architecture SelectIO Resources User Guide (UG571).