I/O Planning for Versal Devices - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)
Document ID
PG202
Release Date
2023-05-16
Version
4.3 English

The MIPI D-PHY GUI does not have I/O Assignment tab for Versal devices. Instead you need to use consolidated I/O planning in the main Vivado IDE Planning that is nibble planner. You can select any I/O for the clock and data lanes in the TX core configuration for the selected XPIO bank.

Table 1. IO Selection for TX Mode depending on Parameters
Line-rate (Mbps) D-PHY IP Parameter

C_EN_DCTS_LOGIC

(Guarantees the clock Rising Edge Alignment to first payload bit on serial lines)

 IO Guidelines
>2500 Disabled (i.e., 0)
Clock Lane
Select the Clock Capable pin ,i.e., 0th pin of a Nibble.
Data Lanes
Select the data lanes such that the propagation of strobe to the TX data pins follows the inter-byte and inter-nibble clocking rules given in the “Clocking" section of Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
>2500 Enabled (i.e., 1)
Clock Lane
Select the Clock Capable pin, i.e., 0th pin of a Nibble.
Data Lanes
Select the data lanes such they are not in the same Nibble as Clock lane Nibble & the propagation of strobe to the TX data pins follows the inter-byte and inter-nibble clocking rules given in the “Clocking” section of Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
<2500 Disabled (i.e., 0) User can select any I/O for the clock and data lanes in the TX core configuration for the selected bank.
<2500 Enabled (i.e., 1) User can select any I/O for the clock and data lanes but the Clock Lane and Data Lanes should not be in the same Nibble.

For the RX core configuration, select the clock capable pin that is 0th Pin ("XCC" and "GC/XCC" pins) of a nibble for the clock lane for the selected XPIO bank.

Select the data lane position depending upon the Clock lane Nibble for the RX core configuration, that is, in the nibble where the clock lane is present and adjacent nibble (Highly recommended). Following is the representation of 4 instances of 4 lane D-PHY in a Bank.

Figure 1. RX Core Configuration

Detailed steps on how to use the Vivado IDE Planning is detailed under section "I/O Planning for Versal Advanced IO Wizard" in Advanced I/O Wizard LogiCORE IP Product Guide (PG320).

While selecting the IOs in a bank across nibbles, users need to ensure the inter-nibble and inter-byte clock guidelines are followed. Refer to the "Clocking" section in Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).

The following figure shows the eight MIPI D-PHY RX cores configured with one clock lane and two data lanes and implemented in a single I/O bank.

The DPHY_RX_MASTER is configured with Include Shared Logic in core option and the remaining cores are configured with Include Shared Logic in example design. The constant clkoutphy signal is generated within the PLL of the DPHY_RX_MASTER core irrespective of the line rate and shared with all other slave IP cores (DPHY_RX_SLAVE1 to DPHY_RX_SLAVE7) with different line rates. The pll_lock signal connection is required for slave IP initialization.

Note: When the master D-PHY RX line rate is < 1500 Mbps, the slave D-PHY RX can be configured with any line rates < = 1500 Mbps, but when the master D-PHY RX line rate is > 1500 Mbps the slave RX should only be configured with matching line rate of master D-PHY RX.
Figure 2. MIPI D-PHY RX Core Shared Logic Use Case for Single I/O Bank