The AMD MIPI D-PHY Controller is designed for transmission and reception of video or pixel data for camera and display interfaces. The core is used as the physical layer for higher level protocols such as the Mobile Industry Processor Interface (MIPI) Camera Serial Interface (CSI-2) and Display Serial Interface (DSI).
This product guide provides information about using, customizing, and simulating the core for AMD UltraScale+™ and 7 series FPGA families as well as AMD Versal™ Adaptive SoCs. It also describes the core architecture and provides details on customizing and interfacing to the core.