Enabling this mode allows the received PPI RX input data to be sent as MIP TX Data duplicated on multiple DPHY TX Interfaces. You can select up to a maximum of 4 TX Interfaces as shown in the following figure. GUI allows to select IO for each interface. You need to ensure that the IOs are exclusive across interfaces. The IOs of each interface can be same or different banks.
Figure 1. MIPI D-PHY – D-PHY Splitter Bridge
This mode is best suited for cases where same camera data needs to be processed by multiple external processing modules. In such cases, the AMD FPGA receives the MIPI stream from the external source (camera) and replicates on multiple output MIPI stream interfaces for further processing by external modules.
Figure 2. D-PHY Splitter Bridge Use Case
