MIPI D-PHY TX (Master) Core Architecture - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)

Document ID
PG202
Release Date
2023-05-16
Version
4.3 English
The following figure shows the MIPI D-PHY TX (Master) core architecture for AMD UltraScale+™ families and AMD Zynq™ UltraScale+™ MPSoC devices. The TX core is partitioned into three major blocks:
TX Physical Coding Sublayer (PCS) Logic
Provides the PPI to the core and generates the necessary controls to the PHY for the lane operation. It also generates entry sequences, line switching between low power and high speed, and performs lane initialization.
TX PHY Logic
Integrates the BITSLICE_CONTROL and TX_BITSLICE in native mode and D-PHY-compatible I/O block. This block does serialization and has clocking implementation for the PHY.
Register Interface
Optional AXI4-Lite register interface to control mandatory protocol timers and registers.
Figure 1. MIPI D-PHY TX (Master) Core Architecture for UltraScale+ Families

The following figure shows the MIPI D-PHY TX (Master) Core Architecture for the 7 series FPGA families.

Figure 2. MIPI D-PHY TX (Master) Core Architecture for 7 Series FPGA Families

The following figure shows the MIPI D-PHY TX (Master) Core Architecture for Versal Adaptive SoC.

Figure 3. MIPI D-PHY TX (Master) Core Architecture for Versal Adaptive SoC