PPI Signals - 4.3 English

This active-High signal indicates that the Lane module (TX or RX) is currently in the Stop state. Also, the protocol can use this signal to indirectly determine if the PHY line levels are in the LP-11 state.

This active-High signal forces the lane module out of “shutdown”. All line drivers, receivers, terminators, and contention detectors are turned off when Enable is Low. When Enable is Low, all other PPI inputs are ignored and all PPI outputs are driven to the default inactive state. Enable is level sensitive and does not depend on any clock.

This active-Low signal is asserted to indicate that the Lane is in the ULP state. For a receiver, this signal indicates that the Lane is in the Ultra Low Power (ULP) state. At the beginning of the ULP state, ulpsactivenot is asserted together with rxulpsesc, or rxclkulpsnot for a clock lane. At the end of the ULP state, this signal becomes inactive to indicate that the Mark-1 state has been observed. Later, after a period of time (Twakeup), the rxulpsesc (or rxclkulpsnot) signal is deasserted.

For clock lanes, this active-High signal causes the lane module to begin transmitting a high-speed clock.

This active-High signal is asserted to cause a clock lane module to enter the ULP state. The lane module remains in this mode until txulpsclk is deasserted.

This active-High signal is asserted when the ULP state is active and the protocol is ready to leave the ULP state. The PHY leaves the ULP state and begins driving Mark-1 after txulpsexit is asserted. The PHY later drives the Stop state (LP-11) when txrequestesc is deasserted. txulpsexit is synchronous to txclkesc. This signal is ignored when the lane is not in the ULP state.

This is used to synchronize PPI signals in the high-speed transmit clock domain. AMD recommends that all transmitting data lane modules share one txbyteclkhs signal. The frequency of txbyteclkhs is exactly 1/8 the high-speed bit rate.

Eight-bit high-speed data to be transmitted. The signal connected to txdatahs[0] is transmitted first. Data is captured on rising edges of txbyteclkhs.

A Low-to-High transition on txrequesths causes the Lane module to initiate a SoT sequence. A High-to-Low transition on txrequest causes the lane module to initiate an EoT sequence. For data lanes, this active-High signal also indicates that the protocol is driving valid data on txdatahs to be transmitted. The lane module accepts the data when both txrequesths and txreadyhs are active on the same rising txbyteclkhs clock edge. The protocol always provides valid transmit data when txrequesths is active. After asserted, txrequesths remains High until the data has been accepted, as indicated by txreadyhs. txrequesths is only asserted while txrequestesc is Low.

This active-High signal indicates that txdatahs[7:0] is accepted by the Lane module to be serially transmitted. txreadyhs is valid on rising edges of txbyteclkhs.

A low-to-high transition on TxSkewCalHS causes the lane module to initiate a deskew calibration. A high-to-low transition on TxSkewCalHS causes the lane module to stop deskew pattern transmission and initiate an EoT sequence

This signal allows the protocol to force a lane module into the Stop state during initialization or following an error situation, such as an expired timeout. When this signal is High, the lane module state machine is immediately forced into the Stop state.

This clock is directly used to generate escape sequences. The period of this clock determines the phase times for low-power signals as defined in the D-PHY specification.

This active-High signal is asserted with txrequestesc to cause the lane module to enter low-power data transmission mode. The Lane module remains in this mode until txrequestesc is deasserted. txulpsesc and all bits of txtriggeresc[3:0] are Low when txlpdtesc is asserted.

This active-High signal is asserted when the ULP state is active and the protocol is ready to leave the ULP state. The PHY leaves the ULP state and begins driving Mark-1 after txulpsexit is asserted. The PHY later drives the Stop state (LP-11) when txrequestesc is deasserted. txulpsexit is synchronous to txclkesc. This signal is ignored when the lane is not in the ULP state.

This active-High signal is asserted with txrequestesc to cause the lane module to enter the ultra-low power state. The lane module remains in this mode until txrequestesc is deasserted. txlpdtesc and all bits of txtriggeresc[3:0] are Low when txulpsesc is asserted.

One of these active-High signals is asserted with txrequestesc to cause the associated trigger to be sent across the lane interconnect. In the receiving lane module, the same bit of rxtriggeresc is then asserted and remains asserted until the lane interconnect returns to the Stop state, which happens when txrequestesc is deasserted at the transmitter. Only one bit of txtriggeresc[3:0] is asserted at any given time, and only when txlpdtesc and txulpsesc are both Low. The following mapping is done by the D-PHY TX module:

• Reset-Trigger→txtriggeresc[3:0] = 4’b0001
• Unknown-3→txtriggeresc[3:0] = 4’b0010
• Unknown-4→txtriggeresc[3:0] = 4’b0100
• Unknown-5→txtriggeresc[3:0] = 4’b1000

This is the eight-bit Escape mode data to be transmitted in low-power data transmission mode. The signal connected to txdataesc[0] is transmitted first. Data is captured on rising edges of txclkesc.

This active-High signal indicates that the protocol is driving valid data on txdataesc[7:0] to be transmitted. The lane module accepts the data when txrequestesc, txvalidesc, and txreadyesc are all active on the same rising txclkesc clock edge.

This active-High signal indicates that txdataesc[7:0] is accepted by the lane module to be serially transmitted. txreadyesc is valid on rising edges of txclkesc.

This asynchronous, active-High signal indicates that a clock lane is receiving a Double Data Rate (DDR) clock signal.

This active-Low signal is asserted to indicate that the clock lane module has entered the ultra-low power state. The lane module remains in this mode with rxulpsclknot asserted until a Stop state is detected on the lane interconnect.

This is used to synchronize signals in the high-speed receive clock domain. The rxbyteclkhs is generated by dividing the received High-Speed DDR clock.

Eight-bit high-speed data received by the lane module. The signal connected to rxdatahs[0] was received first. Data is transferred on rising edges of rxbyteclkhs.

This active-High signal indicates that the lane module is driving data to the protocol on the rxdatahs[7:0] output. There is no rxreadyhs signal, and the protocol is expected to capture rxdatahs[7:0] on every rising edge of rxbyteclkhs where rxvalidhs is asserted. There is no provision for the protocol to slow down (throttle) the receive data.

This active-High signal indicates that the lane module is actively receiving a high-speed transmission from the lane interconnect.

This active-High signal indicates that the Lane module has seen an appropriate synchronization event. rxsynchs is High for one cycle of rxbyteclkhs at the beginning of a high-speed transmission when rxactivehs is first asserted.

This signal allows the protocol to initialize a Lane module and should be released, that is, driven Low, only when the Dp and Dn inputs are in the Stop state for a time T_INIT, or longer.

This signal is used to transfer received data to the protocol during escape mode. This clock is generated from the two low-power signals in the lane interconnect. Because of the asynchronous nature of escape mode data transmission, this clock cannot be periodic.

This active-High signal is asserted to indicate that the lane module is in low-power data receive mode. While in this mode, received data bytes are driven onto the rxdataesc[7:0] output when rxvalidesc is active. The lane module remains in this mode with rxlpdtesc asserted until a Stop state is detected on the lane interconnect.

These active-High signals indicate that a trigger event has been received. The asserted rxtriggeresc[3:0] signal remains active until a Stop state is detected on the lane interconnect. The following mapping is done by the D-PHY RX module:

• Reset-Trigger → rxtriggeresc[3:0] = 4’b0001
• Unknown-3 → rxtriggeresc[3:0] = 4’b0010
• Unknown-4 → rxtriggeresc[3:0] = 4’b0100
• Unknown-5 → rxtriggeresc[3:0] = 4’b1000

This is the eight-bit escape mode low-power data received by the lane module. The signal connected to rxdataesc[0] is received first. Data is transferred on rising edges of rxclkesc.

This active-High signal indicates that the lane module is driving valid data to the protocol on the rxdataesc[7:0] output. There is no rxreadyesc signal, and the protocol is expected to capture rxdataesc[7:0] on every rising edge of rxclkesc where rxvalidesc is asserted. There is no provision for the protocol to slow down (throttle) the receive data.

If the high-speed SoT leader sequence is corrupted, but in such a way that proper synchronization can still be achieved, this active-High signal is asserted for one cycle of rxbyteclkhs. This is considered to be a soft error in the leader sequence and confidence in the payload data is reduced.

If the high-speed SoT leader sequence is corrupted in a way that proper synchronization cannot be expected, this active-High signal is asserted for one cycle of rxbyteclkhs.

If an unrecognized escape entry command is received, this active-High signal is asserted and remains asserted until the next change in line state.

If the number of bits received during a low-power data transmission is not a multiple of eight when the transmission ends, this active-High signal is asserted and remains asserted until the next change in line state.

This active-High signal is asserted when an incorrect line state sequence is detected. For example, if a turn-around request or escape mode request is immediately followed by a Stop state instead of the required Bridge state, this signal is asserted and remains asserted until the next change in line state.