For full details about performance and resource use, visit the Performance and Resource Use web page.
Maximum Frequencies
The maximum frequency of the core operation is dependent on the supported line rates and the speed grade of the devices.Latency
The MIPI D-PHY TX core latency is measured from therequesths signal of the
data lane assertion to the readyhs signal assertion.The MIPI D-PHY RX core latency is the time from the start-of-transmission
(SoT) pattern on the serial lines to the activehs signal
assertion on the PPI. The following table provides the latency numbers for various core
configurations.
Note: To calculate the throughput for higher lanes, multiply
the existing throughput by the configured number of lanes.
| Line Rate (Mbps) | LPX (ns) | Device Family | Lanes | Latency (in byteclkhs 1 cycles) | Data Flow Mode |
|---|---|---|---|---|---|
| 250 | 50 | UltraScale+ | 1 | 10 | D-PHY TX (Master) |
| 500 | 50 | UltraScale+ | 1 | 18 | D-PHY TX (Master) |
| 1,000 | 50 | UltraScale+ | 1 | 33 | D-PHY TX (Master) |
| 1,250 | 50 | UltraScale+ | 1 | 43 | D-PHY TX (Master) |
| 1,500 | 50 | UltraScale+ | 1 | 51 | D-PHY TX (Master) |
| 2,000 | 50 | UltraScale+ | 1 | 67 | D-PHY TX (Master) |
| 2,500 | 50 | UltraScale+ | 1 | 84 | D-PHY TX (Master) |
| 3200 | 50 | Versal Adaptive SoC | 1 | 194 | D-PHY TX (Master) |
| 250 | 50 | UltraScale+ | 1 | 6 | D-PHY RX (Slave) |
| 500 | 50 | UltraScale+ | 1 | 6 | D-PHY RX (Slave) |
| 1,000 | 50 | UltraScale+ | 1 | 6 | D-PHY RX (Slave) |
| 1,250 | 50 | UltraScale+ | 1 | 6 | D-PHY RX (Slave) |
| 1,500 | 50 | UltraScale+ | 1 | 6 | D-PHY RX (Slave) |
| 2,000 | 50 | UltraScale+ | 1 | 6 | D-PHY RX (Slave) |
| 2,500 | 50 | UltraScale+ | 1 | 6 | D-PHY RX (Slave) |
| 3200 | 50 | Versal Adaptive SoC | 1 | 6 | D-PHY RX (Slave) |
| 250 | 50 | 7 series | 1 | 16 | D-PHY TX (Master) |
| 500 | 50 | 7 series | 1 | 24 | D-PHY TX (Master) |
| 1,000 | 50 | 7 series | 1 | 39 | D-PHY TX (Master) |
| 1,250 | 50 | 7 series | 1 | 48 | D-PHY TX (Master) |
| 250 | 50 | 7 series | 1 | 5 | D-PHY RX (Slave) |
| 500 | 50 | 7 series | 1 | 5 | D-PHY RX (Slave) |
| 1,000 | 50 | 7 series | 1 | 5 | D-PHY RX (Slave) |
| 1,250 | 50 | 7 series | 1 | 5 | D-PHY RX (Slave) |
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Throughput
The MIPI D-PHY TX core throughput varies based on line rate, number of data lanes, clock lane mode (continuous or non-continuous) and D-PHY protocol parameters. Throughput is measured from the clock lanetxrequesths signal assertion to the clock lane
txrequesths signal deassertion by transferring a standard
640x480 resolution image as frame data on the PPI. In this measurement, the number of bytes
transfered from the start to the end are taken into account. Data lane txrequesths and txreadyhs
assertion is considered as one-byte transfer. The following table provides the throughput
numbers for various core configurations.
| Line Rate (Mbps) | LPX (ns) | Device Family | Lanes | Throughput (Mbps) | Data Flow Mode |
|---|---|---|---|---|---|
| 250 | 50 | UltraScale+ | 1 | 239 | D-PHY TX (Master) |
| 500 | 50 | UltraScale+ | 1 | 462 | D-PHY TX (Master) |
| 1,000 | 50 | UltraScale+ | 1 | 879 | D-PHY TX (Master) |
| 1,250 | 50 | UltraScale+ | 1 | 1075 | D-PHY TX (Master) |
| 1,500 | 50 | UltraScale+ | 1 | 1261 | D-PHY TX (Master) |
| 2000 | 50 | UltraScale+ | 1 | 1661 | D-PHY TX (Master) |
| 2500 | 50 | UltraScale+ | 1 | 2002 | D-PHY TX (Master) |
| 2936 | 50 | AMD Versal™ Adaptive SoC | 1 | 2212 | D-PHY TX (Master) |
| 3200 | 50 | AMD Versal™ Adaptive SoC | 1 | 2385 | D-PHY TX (Master) |
| 250 | 50 | 7 series | 1 | 231 | D-PHY TX (Master) |
| 500 | 50 | 7 series | 1 | 462 | D-PHY TX (Master) |
| 1,000 | 50 | 7 series | 1 | 879 | D-PHY TX (Master) |
| 1,250 | 50 | 7 series | 1 | 1066 | D-PHY TX (Master) |