The MIPI D-PHY Controller is a physical layer that supports the MIPI CSI-2 and DSI protocols. It is a universal PHY that can be configured as either a transmitter or a receiver. The core consists of an analog front end to generate and receive the electrical level signals, and a digital backend to control the I/O functions.
The MIPI D-PHY Controller provides a point-to-point connection between master and slave, or host and device that comply with a relevant MIPI standard. A typical TX configuration consists of 1 clock lane and 1 to 4 data lanes and a typical RX configuration consists of 1 clock lane and 1 to 8 data lanes. The master/host is primarily the source of data, and the slave/device is usually the sink of data. The D-PHY lanes can be configured for unidirectional lane operation, originating at the master and terminating at the slave. The core can be configured to operate as a master or as a slave. The D-PHY link supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions.
- In HS mode, the low-swing differential signal supports data transfers from 80 Mbps to 3200 Mbps.
- In LP mode, all wires operate as a single-ended line capable of supporting 10 Mbps asynchronous data communications.