Resetting the MIPI D-PHY TX and RX Core - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)
Document ID
PG202
Release Date
2023-05-16
Version
4.3 English
To reset the MIPI D-PHY TX and RX core in a system, perform the following procedure:
  1. Assert core_rst of MIPI D-PHY TX IP core for minimum 40 core_clk cycles.
  2. Assert core_rst of MIPI D-PHY RX IP core for minimum 40 core_clk cycles.
  3. Release the MIPI D-PHY RX core_rst signal.
    Note: When there are multiple instances of D-PHY within the same bank, or when there are TX and RX in same bank, perform the reset removal at same time.
  4. Release the MIPI D-PHY TX core_rst signal.
    Note: When there are multiple instances of D-PHY within the same bank, or when there are TX and RX in same bank, perform the reset removal at same time.
  5. The MIPI D-PHY RX IP core initialization happens after a T_INIT_SLAVE time of 100 μs and is indicated by the assertion of stopstate.
  6. The MIPI D-PHY TX IP core initialization happens after a T_INIT_MASTER time if 1 ms and is indicated by stopstate assertion.
  7. At this point, the MIPI D-PHY TX IP core is ready to accept data from the TX PPI interface.
Note: The impact of the assertion of core_rst on the MIPI D-PHY core is the same as the assertion of the DPHY_EN bit of the CONTROL register.