The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 05/10/2023 Version 4.3 | |
| Core Configuration Tab | Clarified information on 'Guarantees the clock Rising Edge Alignment to first payload bit on serial lines.' |
| I/O Planning for Versal Devices | Updated IP Parameters. |
| Pin and Bank Rules | Added notes for clarification. |
| 04/20/2022 Version 4.3 | |
| MIPI D-PHY RX (Slave) Core Architecture | Update the images in the section. |
| Ultra-Low Power State | Update this section in Protocol Description. |
| Core Configuration Tab | Added the Table 1 table in the section. |
| 06/30/2021 Version 4.3 | |
| I/O Planning for Versal Devices | Updated image. |
| Features | Updated the section. |
| 12/11/2020 Version 4.3 | |
| General Updates | Added information regarding D-PHY support of Versal ACAP. |
| 09/07/2020 Version 4.2 | |
| Pin and Bank Rules | Hot fix to reinstate section. |
| 07/16/2020 Version 4.2 | |
| Core Configuration Tab | Added details of new/updated parameters. |
| Clocking | Added clarifications about MMCM and line rate. |
| PPI Signals | Added new signals. |
| Clocking and Reset Signals | Added new signals. |
| 10/30/2019 Version 4.2 | |
| General Updates | For 7 series fixed mode IDELAY control ready has been incorporated for core operation. |
| General Updates | Added Versal support. |
| 07/02/2019 Version 4.1 | |
| General Updates | Added 2.5 Gb/s support to the subsystem. |
| 12/10/2018 Version 4.1 | |
| General Updates |
|
| 04/04/2018 Version 4.1 | |
| General Updates |
|
| 10/04/2017 Version 4.0 | |
| Minor Updates | Minor Updates |
| 04/05/2017 Version 3.1 | |
| General Updates |
|
| 10/05/2016 Version 3.0 | |
| General Updates |
|
| 04/06/2016 Version 2.0 | |
| General Updates |
|
| 11/18/2015 Version 1.0 | |
| Initial Xilinx release | NA |