Shared Logic provides a flexible architecture that works both as a stand-alone core and as part of a larger design with one of more core instances. This minimizes the amount of HDL modifications required, but at the same time retains the flexibility of the core.
There is a level of hierarchy called <component_name>_support. The following figures show two hierarchies where the shared logic is either contained in the core or in the example design. In these figures, <component_name> is the name of the generated core. The difference between the two hierarchies is the boundary of the core. It is controlled using the Shared Logic option in the Vivado IDE Shared Logic tab for the MIPI D-PHY Controller.
The shared logic comprises an MMCM, a PLL and some BUFGs (maximum of 4).