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There should be at least one MIPI D-PHY IP with Include shared Logic in the Core mode whose outputs for shared resources can be used in other MIPI D-PHY IP generated with Include shared logic in example design mode.
- This is the second MIPI D-PHY core in a multi-core design
- You only want to manage one customization of the MIPI D-PHY core in your design
- You want direct access to the input clocks
To fully utilize the MMCM and PLL, customize one MIPI D-PHY core with shared logic in the core and one with shared logic in the example design. You can connect the MMCM/PLL outputs from the first MIPI D-PHY core to the second core.
If you want fine control you can select Include shared logic in example design and base your own logic on the shared logic produced in the example design.
Following things should also be taken into consideration while connecting Master & Slave cores:
- Master and slave cores should have the same CLKOUTPHY clock frequency.
- TX master and slave cores should be configured with the same line rate when sharing clock resources.
- RX master and slave cores with line-rate 1500 Mbps or less can share clock resources.
- RX master and slave cores with the same line-rate (greater than 1500 Mbps) can share clock resources.
- Additionally MIPI D-PHY TX can share master/slave clock resources, only if the TXCLKESC is configured with the same clock frequency.