Test Bench - 4.3 English

MIPI D-PHY LogiCORE IP Product Guide (PG202)
Document ID
PG202
Release Date
2023-05-16
Version
4.3 English

This chapter contains information about the example design provided in the AMD Vivado™ Design Suite.

The MIPI D-PHY Controller delivers a demonstration test bench for the example design. This chapter describes the MIPI D-PHY Controller test bench and its functionality. The test bench consists of the following modules:
  • Device Under Test (DUT)
  • Clock and reset generator
  • Status monitor
The example design demonstration test bench is a simple Verilog module to exercise the example design and the core itself. It simulates an instance of the MIPI D-PHY TX example design that is externally looped back to the MIPI D-PHY RX example design. The following figure shows the MIPI D-PHY Controller test bench where DUT1 is configured as D-PHY TX, and DUT2 is configured as D-PHY RX.

The MIPI D-PHY Controller test bench generates all the required clocks and resets, and waits for successful data pattern checking to complete. If it fails to detect successful data pattern checking, it produces an error.

Note: Example design for AMD Versal™ Adaptive SoC is supported only when the Example design is in the core.
Figure 1. MIPI D-PHY Test Bench