The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).
| Vivado IDE Parameter/Value | User Parameter/Value | Default Value |
|---|---|---|
| Core Parameters | ||
| D-PHY Lanes | C_DPHY_LANES | 1 |
| Line Rate (Mb/s) | C_LINE_RATE | 1,000 |
| Data Flow Mode | C_DATA_FLOW | Master (TX) |
| Escape Clk (MHz) | C_ESC_CLK_PERIOD | 20.000 |
| LPX (ns) | C_LPX_PERIOD | 50 |
| D-PHY RX ULPS WAKEUP counter for 1ms time | C_EN_ULPS_WAKEUP_CNT | False |
| IODELAY_GROUP name | C_IDLY_GROUP_NAME | mipi_dphy_idly_group |
| Enable the SSC clock | C_EN_SSC | False |
| Guarantees the rising edge clock alignment to first payload data bit | C_EN_DCTS_LOGIC | False |
| External IDELAY tap loading | C_EN_EXT_TAP | False |
| Protocol Watchdog Timers | ||
| Enable Deskew Sequence detection Logic | C_RCVE_DESKEW | 0 |
| Enable HS and ESC timeout counters/Registers | C_EN_TIMEOUT_REGS | 0 |
| HS Timeout (Bytes) | C_HS_TIMEOUT | 65,541 |
| Escape Timeout (ns) | C_ESC_TIMEOUT | 25,600 |
| Debug and Control | ||
| Enable Register Interface | C_EN_REGIF | 0 |
| OBUFTDS Inference | C_EN_HS_OBUFTDS | 0 |
| Active Lane Support | C_EN_ACT_LANES | 0 |
| HS_SETTLE Parameter (ns) | C_HS_SETTLE_NS | 145 |
| Internal MMCM | C_EXT_MMCM | 0 |
| External MMCM | C_EXT_MMCM | 1 |