1588v2 Timestamping - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

The integrated block for the 100G Ethernet IP core supports 1588v2 timestamping. All the necessary signals are provided to allow external soft logic to make precise corrections to the timestamp captured by the IP. The core supports 1-step and 2-step 1588v2 clocks through ingress and egress timestamp captures.

According to the IEEE 1588v2 standard, there are various PTP message encapsulations [Ref 1] . In the case of 2-step clocks, all types of encapsulation are possible with the 100G Ethernet IP core if the design includes a PTP-specific (software) implementation.

Inputs are provided for the timestamp offset value in the message, and for the RX path timestamp to use for the field adjustment. Further details on the function of the command fields are found in Table: Transceiver I/O .