AXI4-Lite Interface Implementation - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

If you want to instantiate AXI4-Lite interface to access the control and status registers of the core, select Include AXI4-Lite Control and Statistics Interface in the General tab. It enables the cmac_usplus_0_axi4_lite_if_wrapper module (that contains cmac_usplus_0_axi4_lite_reg_map along with the cmac_usplus_0_axi4_lite_slave_2_ipif module) in cmac_usplus_0_wrapper . The user interface logic ( cmac_usplus_0_axi4_lite_user_if ) for accessing the registers (control, status and statistics) is present in the cmac_usplus_0_pkt_gen_mon module.

Note: In case of CAUI-4 mode, if you select the Include IEEE 802.3bj RS-FEC and Include AXI4-Lite Control and Statistics Interface options, the RS-FEC control and statistics registers are accessible for write and read in the cmac_usplus_0_axi4_lite_reg_map module.

This mode enables the following features:

You can configure all the CTL ports of the core through AXI4-Lite interface. This operation is performed by writing to a set of address locations with the required data to the register map interface. The address location with the configuration register list is mentioned in Table: Configuration Register Map .

You can access all the status and statistics registers from the core through AXI4-Lite interface. This is performed by reading the address locations for the status and statistics registers through register map. Table: Status and Statistics Register Map shows the address with the corresponding register descriptions.

The following diagram shows the implementation when Include AXI4-Lite Control and Statistics Interface is selected.

Figure 5-12: Example Design Hierarchy with AXI4-Lite Interface

X-Ref Target - Figure 5-12

X16361-pg203-example-design-hier-axi4-lite.jpg