Data is transferred in a segment on the TX interface when the corresponding tx_enainS is a value of 1. The TX interface buffers data, but packets must be written in their entirety unless back pressure is applied (see Gaps). Therefore, it is acceptable to have clock cycles in which none of the tx_enainS signals are active during backpressure. However, during a clock cycle with tx_enain0 active, segments must be filled in sequence with no gaps between active segments. The following are some of the illegal combinations of tx_enainS:
•tx_enain0=0, tx_enain1=1, tx_enain2=1, tx_enain3=1
•tx_enain0=1, tx_enain1=0, tx_enain2=1, tx_enain3=1
•tx_enain0=1, tx_enain1=1, tx_enain2=0, tx_enain3=1
Data is transferred in a segment on the RX interface when the corresponding rx_enainS is a value of 1. Similarly, the RX interface buffers data and does not forward until it has a sufficient quantity. Therefore, there are clock cycles in which none of the rx_enainS signals are active.