Base Pages - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

The register map is broken into two 512-base address pages to allow for future development and expansion.

Table 5-4: Register Base Addresses

Base Address

Space Name

0x0000 0000

IP Configuration Registers

0x0000 0200

Status and Statistics Registers

All registers are 32 Bytes in size, and aligned on 32 Byte addressing. In the below register space maps, any holes in the address space should be considered RESERVED and can cause the AXI Interface Controller IP to respond with an error if accessed.