CMAC/GT Selections and Configuration Tab - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

This CMAC/GT Selection and Configuration tab, shown in This Figure , is used to configure transceiver resources. The window loads with default values that are pre-populated.

Figure 4-3: CMAC/GT Selections and Configuration Tab

X-Ref Target - Figure 4-3

GUI_snap_tab_3.PNG

Table: GT Selections and Configuration Tab describes the GT Selection and Configuration tab options.

Table 4-3: GT Selections and Configuration Tab

Parameter

Description

Default Value

Range

GT Location

GT Location Selection

Select whether the GT IP is included in the core or in the example design

Include GT subcore in core

Include GT subcore in core

Include GT subcore in example design

CMAC Lane to Transceiver Association

CMAC Core Selection

Select 100G Ethernet Hard IP core location

Based on the FPGA, part number, CMAC Mode and GT type selected

Based on the FPGA, part number, CMAC Mode and GT type selected, all the usable/configurable 100G Ethernet IP cores for that particular device/package will be listed.

GT Group Selection

Select the GT Group

Based on the FPGA, part

number, CMAC Mode, GT type selected and also based on GT selection guidelines

Based on the FPGA, part

number, CMAC Mode, GT type selected and also based on GT selection guidelines.

Lane-00 to Lane-09

Auto fill GT lanes based on the GT Group selected

The best combination of transceivers will be auto filled based on the 100G Ethernet IP core location chosen

Based on the Mode selection (CAUI-10, CAUI-4, 100GAUI-2, or Runtime Switchable), the GT selection guidelines are followed. See Transceiver Selection Rules for more details.

Shared Logic

Include Shared Logic in

Determines the location of the transceiver shared logic

Core

Core

Example Design

Advanced Options

Receiver

RX Insertion Loss at Nyquist (dB)

Specify the insertion loss of the channel between the transmitter and receiver at the Nyquist frequency in dB.

Note: This option is available for Duplex and Simplex RX operation.

12

Depends on GT

RX Equalization Mode

When Auto is specified, the equalization mode implemented by the Wizard depends on the value specified for insertion loss at Nyquist. Refer to Xilinx UG576/UG578 to determine the appropriate equalization mode for your system.

Note: This option is available for Duplex and Simplex RX operation. This feature is selected as Auto with grayed out for the GTM transceiver type.

Auto

Auto

DFE

LPM

Clocking Options

RX GT Buffer

Controls whether the GT receiver elastic buffer bypass operates in multi-lane mode or single-lane mode.

Note: This option is available for Duplex and Simplex RX operation. This feature is not applicable for the GTM transceiver type.

Enable

Enable

Bypass

RX GT Buffer Bypass Mode

RX GT Buffer Bypass Mode.

RX GT Buffer Bypass Mode is Multi-Lane when the RX GT Buffer option is set to Enable .
RX GT Buffer Bypass Mode is Single-Lane when the RX GT Buffer option is set to Bypass .

Note: This option is available for Duplex and Simplex RX operation. This feature is not applicable for the GTM transceiver type.

Multi-Lane

Multi-Lane

Single-Lane

GT QPLL

PLL Type

GT PLL Type

Note: This feature is not applicable for the GTM transceiver type.

QPLL0

QPLL0

QPLL1

Others

Enable Pipeline Register

Selecting this option will include one stage pipeline register between the CMAC core and the GT to ease timing.

0

0: Disable

1: Enable

Enable Additional GT Control/Status and DRP Ports

Enable Additional GT Control/Status and DRP Ports

0

0: Disable

1: Enable