CORE XCI Top Level Port List - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

The top level port list for the core XCI with all features enabled is shown in Table: CORE XCI Top Level Port List .

Table 5-2: CORE XCI Top Level Port List

Name

Size

I/O

Description

sys_reset

1

I

Reset for the CMAC core.

gt_ref_clk_p

1

I

Differential input clk to GT.

gt_ref_clk_n

1

I

Differential input clk to GT.

init_clk

1

I

Stable and free-running clk input to GT. Used as the clock for the GT reset state machines, and the GT Channel and Common DRP ports, if included.

gt_loopback_in

30/12

I

GT loopback input signal. Refer to the applicable GT user guide [Ref 15] [Ref 16] .

Port width: 30-bit width for CAUI-10 or Runtime Switchable case, and 12-bit width for CAUI-4/100GAUI-4 mode.

gt_rxrecclkout

10/4

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Port width: 10-bit width for CAUI-10 or Runtime Switchable case, and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_ref_clk_out

1

O

GT reference clock output.

gt_powergoodout

10/4

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Port width: 10-bit width for CAUI-10 or Runtime Switchable case, and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_rxp_in

10/4

I

Differential serial GT RX input.

Port width: 10-bit width for CAUI-10 or Runtime Switchable case, and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_rxn_in

10/4

I

Differential serial GT RX input.

Port width: 10-bit width for CAUI-10 or Runtime Switchable case, and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_txp_out

10/4

O

Differential serial GT TX output.

Port width: 10-bit width for CAUI-10 or Runtime Switchable case, and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_txn_out

10/4

O

Differential serial GT TX output.

Port width: 10-bit width for CAUI-10 or Runtime Switchable case, and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_txusrclk2

1

O

TX user clock output from GT.

gt_rxusrclk2

1

O

RX user clock output from GT.

rx_clk

1

I

RX clock input.

tx_clk

1

I

TX clock input.

Note: This port is available when Include GT subcore in example design is selected from the CMAC/ GT Selection and Configuration tab.

core_rx_reset

1

I

RX reset input to the core.

Note: This input is 2-stage synchronized with the respective clock inside the core.

core_tx_reset

1

I

TX reset input to the core.

Note: This input is 2-stage synchronized with the respective clock inside the core.

usr_rx_reset

1

O

RX reset output for the user logic.

usr_tx_reset

1

O

TX reset output for the user logic.

core_drp_reset

1

I

Core DRP reset.

Note: This input is 2-stage synchronized with the respective clock inside the core.

gtwiz_userdata_tx_in

320

O

GT TX user data out when GT is present in example design

Note: This port is available for the CAUI-10 configuration when Include GT subcore in example design is selected from the CMAC/ GT Selection and Configuration tab.

gtwiz_userdata_rx_out

320

I

GT RX user data in when GT is present in example design

Note: This port is available for the CAUI-10 configuration when Include GT subcore in example design is selected from the CMAC/ GT Selection and Configuration tab.

txdata_in

1280

O

GT TX user data out when GT is present in example design

Note: This port is available for CAUI-4/Runtime Switchable configurations when Include GT subcore in example design is selected from the CMAC/ GT Selection and Configuration tab.

txctrl0_in

160

O

GT TX user control output

Note: This port is available for CAUI-4/Runtime Switchable configurations when Include GT subcore in example design is selected from the CMAC/ GT Selection and Configuration tab.

txctrl1_in

160

O

GT TX user control output

Note: This port is available for CAUI-4/Runtime Switchable configurations when Include GT subcore in example design is selected from the CMAC/ GT Selection and Configuration tab.

rxdata_out

1280

I

GT RX user data in when GT is present in example design

Note: This port is available for CAUI-4/Runtime Switchable configurations when Include GT subcore in example design is selected from the CMAC/ GT Selection and Configuration tab.

rxctrl0_out

160

I

GT RX user control input

Note: This port is available for CAUI-4/Runtime Switchable configurations when Include GT subcore in example design is selected from the CMAC/ GT Selection and Configuration tab.

rxctrl1_out

160

I

GT RX user control input

Note: This port is available for CAUI-4/Runtime Switchable configurations when Include GT subcore in example design is selected from the CMAC/ GT Selection and Configuration tab.

gt_eyescanreset

10/4

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case and 4-bit for CAUI-4/100GAUI-4 mode.

gt_eyescantrigger

10/4

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_rxcdrhold

10/4

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_rxpolarity

10/4

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC / GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_rxrate

30/12

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 30-bit for CAUI-10 or Runtime Switchable case and 12-bit width for CAUI-4/100GAUI-4 mode.

gt_txdiffctrl

50/20

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 50-bit for CAUI-10 or Runtime Switchable case and 20-bit width for CAUI-4/100GAUI-4 mode.

gt_txpolarity

10/4

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_txinhibit

10/4

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case, and 20-bit width for CAUI-4/100GAUI-4 mode.

gt_txpippmen

10/4

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case, and 20-bit width for CAUI-4/100GAUI-4 mode.

gt_txpippmsel

10/4

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case, and 20-bit width for CAUI-4/100GAUI-4 mode.

gt_txpostcursor

50/20

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 50-bit for CAUI-10 or Runtime Switchable case, and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_txprbsforceerr

10/4

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_txprecursor

50/20

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 50-bit for CAUI-10 or Runtime Switchable case and 20-bit width for CAUI-4/100GAUI-4 mode.

gt_eyescandataerror

10/4

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_txbufstatus

20/8

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 20-bit for CAUI-10 or Runtime Switchable case and 8-bit width for CAUI-4/100GAUI-4 mode.

gt_rxdfelpmreset

10/4

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_rxlpmen

10/4

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_rxprbscntreset

10/4

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_rxprbserr

10/4

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_rxprbssel

40/16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 40-bit for CAUI-10 or Runtime Switchable case and 16-bit width for CAUI-4/100GAUI-4 mode.

gt_rxresetdone

10/4

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_txprbssel

40/16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 40-bit for CAUI-10 or Runtime Switchable case and 16-bit width for CAUI-4/100GAUI-4 mode.

gt_txresetdone

10/4

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 10-bit for CAUI-10 or Runtime Switchable case and 4-bit width for CAUI-4/100GAUI-4 mode.

gt_rxbufstatus

30/12

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

Port width: 30-bit for CAUI-10 or Runtime Switchable case and 12-bit width for CAUI-4/100GAUI-4 mode.

gtwiz_reset_tx_datapath

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

gtwiz_reset_rx_datapath

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

gt_drpclk

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt0_drpen

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt0_drpwe

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt0_drpaddr

10

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt0_drpdi

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt0_drpdo

16

O

Refer to the applicable GT user guide for the port description.

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt0_drprdy

1

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt1_drpen

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt1_drpwe

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt1_drpaddr

10

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt1_drpdi

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt1_drpdo

16

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt1_drprdy

1

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt2_drpen

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt2_drpwe

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt2_drpaddr

10

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt2_drpdi

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt2_drpdo

16

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt2_drprdy

1

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt3_drpen

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt3_drpwe

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt3_drpaddr

10

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt3_drpdi

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt3_drpdo

16

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt3_drprdy

1

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

gt4_drpen

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt4_drpwe

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt4_drpaddr

10

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt4_drpdi

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt4_drpdo

16

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt4_drprdy

1

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt5_drpen

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt5_drpwe

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt5_drpaddr

10

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt5_drpdi

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt5_drpdo

16

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt5_drprdy

1

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt6_drpen

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt6_drpwe

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt6_drpaddr

10

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt6_drpdi

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt6_drpdo

16

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt6_drprdy

1

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt7_drpen

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt7_drpwe

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt7_drpaddr

10

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt7_drpdi

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt7_drpdo

16

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt7_drprdy

1

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt8_drpen

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt8_drpwe

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt8_drpaddr

10

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt8_drpdi

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt8_drpdo

16

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt8_drprdy

1

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt9_drpen

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt9_drpwe

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt9_drpaddr

10

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt9_drpdi

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt9_drpdo

16

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

gt9_drprdy

1

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

common0_drpaddr

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

common0_drpdi

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

common0_drpwe

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

common0_drpen

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

common0_drprdy

1

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

common0_drpdo

16

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab.

common1_drpaddr

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

common1_drpdi

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

common1_drpwe

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

common1_drpen

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

common1_drprdy

1

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

common1_drpdo

16

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case for CAUI-10 or Runtime Switchable case.

common2_drpaddr

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

common2_drpdi

16

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

common2_drpwe

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

common2_drpen

1

I

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

common2_drprdy

1

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

common2_drpdo

16

O

Refer to the applicable GT user guide for the port description [Ref 15] [Ref 16] .

Note: This port is available when Enable Additional GT Control/Status and DRP Ports is selected from the CMAC/ GT Selection and Configuration tab for CAUI-10 or Runtime Switchable case.

tx_reset_done

1

I

TX reset done input to the core from the reset wrapper logic.

Note: This port is available when the Include Shared Logic in option is set to Example Design in the CMAC/ GT Selection and Configuration tab.

rx_reset_done

1

I

RX reset done input to the core from the reset wrapper logic.

Note: This port is available when the Include Shared Logic in option is set to Example Design in the CMAC/ GT Selection and Configuration tab.

rx_serdes_reset_done

10

I

RX SerDes reset done input to the core from the reset wrapper logic.

Note: This port is available when the Include Shared Logic in option is set to Example Design in the CMAC/ GT Selection and Configuration tab.

tx_reset_done_sync

1

I

Synchronized TX reset done input to the core from the reset wrapper logic.

Note: This port is available when the Include Shared Logic in option is set to Example Design in the CMAC/ GT Selection and Configuration tab.

rx_reset_done_sync

1

I

Synchronized RX reset done input to the core from the reset wrapper logic.

Note: This port is available when the Include Shared Logic in option is set to Example Design in the CMAC/ GT Selection and Configuration tab, and the core Operation is set to Simplex RX in the General tab.

gt_reset_tx_done_out

1

O

TX reset done out from the GT.

Note: This port is available when the Include Shared Logic in option is set to Example Design in the CMAC/ GT Selection and Configuration tab.

gt_reset_rx_done_out

1

O

RX reset done out from the GT.

Note: This port is available when the Include Shared Logic in option is set to Example Design in the CMAC/ GT Selection and Configuration tab.

axi_usr_tx_reset

1

O

User TX reset from the AXI4-Lite register map module.

Note: This port is available when the Include Shared Logic in option is set to Example Design in the CMAC/ GT Selection and Configuration tab, and Include AXI4-Lite Control and Statistics Interface is selected in the General tab.

axi_usr_rx_reset

1

O

User RX reset from the AXI4-Lite register map module.

Note: This port is available when the Include Shared Logic in option is set to Example Design in the CMAC/ GT Selection and Configuration tab, and Include AXI4-Lite Control and Statistics Interface is selected in the General tab.

axi_usr_rx_serdes_reset

10

O

User RX SerDes reset from the AXI4-Lite register map module.

Note: This port is available when the Include Shared Logic in option is set to Example Design in the CMAC/ GT Selection and Configuration tab, and Include AXI4-Lite Control and Statistics Interface is selected in the General tab.

axi_gt_reset_all

1

O

Reset signal to GT from the AXI4-Lite register map module.

Note: This port is available when the Include GT subcore in example design option is selected in the CMAC/ GT Selection and Configuration tab and Include AXI4-Lite Control and Statistics Interface is selected in the General tab.

ctl_gt_loopback

1

O

Loopback signal to GT from the AXI4-Lite register map module.

Note: This port is available when the Include GT subcore in example design option is selected in the CMAC/ GT Selection and Configuration tab and Include AXI4-Lite Control and Statistics Interface is selected in the General tab.

rx_serdes_clk

10

O

RX SerDes clock out from the core to the reset wrapper.

Note: This port is available when Include GT subcore in core is selected and Include Shared Logic option is set to Example Design in the CMAC/ GT Selection and Configuration tab.

rx_serdes_clk_in

10

I

RX SerDes clock input to the core.

Note: This port is available when the Include GT subcore in example design option is selected in the CMAC/ GT Selection and Configuration tab.

qpll0clk_in

10/4

I

QPLL0 clock input. Port width:

10-bit for CAUI-10 or Runtime Switchable case.

4-bit width for CAUI-4/100GAUI-4 mode.

Note: This port is available when the Include Shared Logic in option is set to Example Design in the CMAC/ GT Selection and Configuration tab.

qpll0refclk_in

10/4

I

QPLL0 ref clock input. Port width:

10-bit for CAUI-10 or Runtime Switchable case.

4-bit width for CAUI-4/100GAUI-4 mode.

Note: This port is available when the Include Shared Logic in option is set to Example Design in the CMAC/ GT Selection and Configuration tab.

qpll1clk_in

10/4

I

QPLL1 clock input. Port width:

10-bit for CAUI-10 or Runtime Switchable case.

4-bit width for CAUI-4/100GAUI-4 mode.

Note: This port is available when the Include Shared Logic in option is set to Example Design in the CMAC/ GT Selection and Configuration tab.

qpll1refclk_in

10/4

I

QPLL1 ref clock input. Port width:

10-bit for CAUI-10 or Runtime Switchable case.

4-bit width for CAUI-4/100GAUI-4 mode.

Note: This port is available when the Include Shared Logic in option is set to Example Design in the CMAC/ GT Selection and Configuration tab.

gtwiz_reset_qpll0lock_in

3/1

I

QPLL0 lock reset input to the GT. Port width:

3-bit for CAUI-10 or Runtime Switchable case.

1-bit width for CAUI-4/100GAUI-4 mode.

Note: This port is available when the Include Shared Logic in option is set to Example Design , and PLL Type is set to QPLL0 in the CMAC/ GT Selection and Configuration tab.

gtwiz_reset_qpll0reset_out

3/1

O

QPLL0 lock reset output from the GT. Port width:

3-bit for CAUI-10 or Runtime Switchable case.

1-bit width for CAUI-4/100GAUI-4 mode.

Note: This port is available when the Include Shared Logic in option is set to Example Design , and PLL Type is set to QPLL0 in the CMAC/ GT Selection and Configuration tab.

gtwiz_reset_qpll1lock_in

3/1

I

QPLL1 lock reset input to the GT. Port width:

3-bit for CAUI-10 or Runtime Switchable case.

1-bit width for CAUI-4/100GAUI-4 mode.

Note: This port is available when the Include Shared Logic in option is set to Example Design , and PLL Type is set to QPLL1 in the CMAC/ GT Selection and Configuration tab.

gtwiz_reset_qpll1reset_out

3/1

O

QPLL1 lock reset output from the GT. Port width:

3-bit for CAUI-10 or Runtime Switchable case.

1-bit width for CAUI-4/100GAUI-4 mode.

Note: This port is available when the Include Shared Logic in option is set to Example Design , and PLL Type is set to QPLL1 in the CMAC/ GT Selection and Configuration tab.

rx_dataout0

128

O

Receive segmented LBUS Data for segment 0. The value of this bus is only valid in cycles that rx_enaout0 is sampled as 1.

rx_dataout1

128

O

Receive segmented LBUS data for segment1.

rx_dataout2

128

O

Receive segmented LBUS data for segment2.

rx_dataout3

128

O

Receive segmented LBUS data for segment3.

rx_enaout0

1

O

Receive LBUS enable for segment0. This signal qualifies the other signals of the RX segmented LBUS interface. Signals of the RX LBUS Interface are only valid in cycles in which rx_enaout is sampled as a 1.

rx_enaout1

1

O

Receive LBUS enable for segment1.

rx_enaout2

1

O

Receive LBUS enable for segment2.

rx_enaout3

1

O

Receive LBUS enable for segment3.

rx_sopout0

1

O

Receive LBUS start of packet (SOP). for segment0. This signal indicates the SOP when it is sampled as a 1 and is only valid in cycles in which rx_enaout is sampled as a 1.

rx_sopout1

1

O

Receive LBUS SOP for segment1.

rx_sopout2

1

O

Receive LBUS SOP for segment2.

rx_sopout3

1

O

Receive LBUS SOP for segment3.

rx_eopout0

1

O

Receive LBUS end of packet (EOP). for segment0. This signal indicates the EOP when it is sampled as a 1 and is only valid in cycles in which rx_enaout is sampled as a 1.

rx_eopout1

1

O

Receive LBUS EOP for segment1.

rx_eopout2

1

O

Receive LBUS EOP for segment2.

rx_eopout3

1

O

Receive LBUS EOP for segment3.

rx_errout0

1

O

Receive LBUS error for segment0. This signal indicates that the current packet being received has an error when it is sampled as a 1. This signal is only valid in cycles when both rx_enaout and rx_eopout are sampled as a 1. When this signal is a value of 0, it indicates that there is no error in the packet being received.

rx_errout1

1

O

Receive LBUS error for segment1.

rx_errout2

1

O

Receive LBUS error for segment2.

rx_errout3

1

O

Receive LBUS error for segment3.

rx_mtyout0

4

O

Receive LBUS empty for segment0. This bus indicates how many bytes of the rx_dataout bus are empty or invalid for the last transfer of the current packet. This bus is only valid in cycles when both rx_enaout and rx_eopout are sampled as 1. When rx_errout and rx_enaout are sampled as 1, the value of rx_mtyout[2:0] is always 000. Other bits of rx_mtyout are as usual.

rx_mtyout1

4

O

Receive LBUS empty for segment1.

rx_mtyout2

4

O

Receive LBUS empty for segment2.

rx_mtyout3

4

O

Receive LBUS empty for segment3.

tx_rdyout

1

O

Transmit LBUS ready. This signal indicates whether the dedicated 100G Ethernet IP core TX path is ready to accept data and provides back-pressure to the user logic.

A value of 1 means the user logic can pass data to the 100G Ethernet IP core. A value of 0 means the user logic must stop transferring data to the 100G Ethernet IP core within four cycles or there will be an overflow.

tx_ovfout

1

O

Transmit LBUS overflow. This signal indicates whether you have violated the back-pressure mechanism provided by the tx_rdyout signal. If tx_ovfout is sampled as a 1, a violation has occurred. It is up to you to design the rest of the user logic to not overflow the TX interface. In the event of an overflow condition, the TX path must be reset.

tx_unfout

1

O

Transmit LBUS underflow. This signal indicates whether you have under-run the LBUS interface. If tx_unfout is sampled as 1, a violation has occurred meaning the current packet is corrupted. Error control blocks are transmitted as long as the underflow condition persists.

It is up to the user logic to ensure a complete packet is input to the core without under-running the LBUS interface.

tx_datain0

128

I

Transmit segmented LBUS data for segment0. This bus receives input data from the user logic. The value of the bus is captured in every cycle that tx_enain is sampled as 1.

tx_datain1

128

I

Transmit segmented LBUS data for segment1.

tx_datain2

128

I

Transmit segmented LBUS data for segment2.

tx_datain3

128

I

Transmit segmented LBUS data for segment3.

tx_enain0

1

I

Transmit LBUS enable for segment0. This signal is used to enable the TX LBUS interface. All signals on this interface are sampled only in cycles in which tx_enain is sampled as a 1.

tx_enain1

1

I

Transmit LBUS enable for segment1.

tx_enain2

1

I

Transmit LBUS enable for segment2.

tx_enain3

1

I

Transmit LBUS enable for segment3.

tx_sopin0

1

I

Transmit LBUS SOP for segment0. This signal is used to indicate the SOP when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles in which tx_enain is sampled as a 1.

tx_sopin1

1

I

Transmit LBUS SOP for segment1.

tx_sopin2

1

I

Transmit LBUS SOP for segment2.

tx_sopin3

1

I

Transmit LBUS SOP for segment3.

tx_eopin0

1

I

Transmit LBUS EOP for segment0. This signal is used to indicate the EOP when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles in which tx_enain is sampled as a 1.

tx_eopin1

1

I

Transmit LBUS EOP for segment1.

tx_eopin2

1

I

Transmit LBUS EOP for segment2.

tx_eopin3

1

I

Transmit LBUS EOP for segment3.

tx_errin0

1

I

Transmit LBUS error for segment0. This signal is used to indicate a packet contains an error when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles in which tx_enain and tx_eopin are sampled as 1. When this signal is sampled as a 1, the last data word is replaced with the IEEE standard 802.3-2012 Error Code control word that guarantees the partner device receives the packet in error. If a packet is input with this signal set to a 1, the FCS checking and reporting is disabled (only for that packet).

tx_errin1

1

I

Transmit LBUS error for segment1.

tx_errin2

1

I

Transmit LBUS error for segment2.

tx_errin3

1

I

Transmit LBUS error for segment3.

tx_mtyin0

4

I

Transmit LBUS empty for segment0. This bus is used to indicate how many bytes of the tx_datain bus are empty or invalid for the last transfer of the current packet. This bus is sampled only in cycles that tx_enain and tx_eopin are sampled as 1. When tx_eopin and tx_errin are sampled as 1, the value of tx_mtyin[2:0] is ignored as treated as if it was 000. The other bits of tx_mtyin are used as usual.

tx_mtyin1

4

I

Receive LBUS empty for segment1.

tx_mtyin2

4

I

Receive LBUS empty for segment2.

tx_mtyin3

4

I

Receive LBUS empty for segment3.

tx_axis_tdata

512

I

512-bit TX AXI4-Stream data input.

Note: This port is available when the User Interface option is selected as AXIS in the General tab.

tx_axis_tvalid

1

I

AXI4-Stream Data Valid input.

Note: This port is available when the User Interface option is selected as AXIS in the General tab.

tx_axis_tready

1

O

AXI4-Stream acknowledge signal to indicate to start the data transfer.

Note: This port is available when the User Interface option is selected as AXIS in the General tab.

tx_axis_tlast

1

I

AXI4-Stream signal indicating end of Ethernet packet.

Note: This port is available when the User Interface option is selected as AXIS in the General tab.

tx_axis_tkeep

64

I

AXI4-Stream Data Control. tx_axis_tkeep word signifying valid data on tx_axis_tdata.

Note: This port is available when the User Interface option is selected as AXIS in the General tab.

tx_axis_tuser

1

O

AXI4-Stream User Sideband interface. Equivalent to the tx_errin signal.

1 = indicates a bad packet

0 = indicates a good packet

Note: This port is available when the User Interface option is selected as AXIS in the General tab.

rx_axis_tdata

512

O

512-bit RX AXI4-Stream data output.

Note: This port is available when the User Interface option is selected as AXIS in the General tab.

rx_axis_tvalid

1

O

AXI4-Stream Data Valid

Note: This port is available when the User Interface option is selected as AXIS in the General tab.

rx_axis_tlast

1

O

AXI4-Stream signal indicating an end of packet.

Note: This port is available when the User Interface option is selected as AXIS in the General tab.

rx_axis_tkeep

64

O

AXI4-Stream Data Control to upper layer. rx_axis_tkeep word signifying valid data on rx_axis_tdata.

Note: This port is available when the User Interface option is selected as AXIS in the General tab.

rx_axis_tuser

1

O

AXI4-Stream User Sideband interface.

1 = indicates a bad packet has been received

0 = indicates a good packet has been received

Note: This port is available when the User Interface option is selected as AXIS in the General tab.

ctl_tx_enable

1

I

TX Enable. This signal is used to enable the transmission of data when it is sampled as a 1. When sampled as a 0, only idles are transmitted by CMAC. This input should not be set to 1 until the receiver it is sending data to (that is, the receiver in the other device) is fully aligned and ready to receive data (that is, the other device is not sending a remote fault condition). Otherwise, loss of data can occur. If this signal is set to 0 while a packet is being transmitted, the current packet transmission is completed and then the CMAC stops transmitting any more packets.

ctl_tx_send_lfi

1

I

Transmit Local Fault Indication (LFI) code word. If this input is sampled as a 1, the TX path only transmits Local Fault code words.

ctl_tx_send_rfi

1

I

Transmit Remote Fault Indication (RFI) code word. If this input is sampled as a 1, the TX path only transmits Remote Fault code words. This input should be set to 1 until the RX path is fully aligned and is ready to accept data from the link partner.

ctl_tx_send_idle

1

I

Transmit Idle code words. If this input is sampled as a 1, the TX path only transmits Idle code words. This input should be set to 1 when the partner device is sending Remote Fault Indication (RFI) code words.

stat_tx_local_fault

1

O

A value of 1 indicates the receive decoder state machine is in the TX_INIT state. This output is level sensitive.

ctl_rx_enable

1

I

RX Enable. For normal operation, this input must be set to 1. When this input is set to 0, after the RX completes the reception of the current packet (if any), it stops receiving packets by keeping the PCS from decoding incoming data. In this mode, there are no statistics reported and the LBUS interface is idle.

ctl_rx_force_resync

1

I

RX force resynchronization input. This signal is used to force the RX path to reset, re-synchronize, and realign. A value of 1 forces the reset operation. A value of 0 allows normal operation.

Note: This input should normally be Low and should only be pulsed (one cycle minimum pulse) to force realignment.

stat_rx_framing_err_0

2

O

RX sync header bits framing error for lane 0. Each PCS Lane has a two-bit bus that indicates how many sync header errors were received for that PCS Lane. The value of the bus is only valid when the corresponding stat_rx_framing_err_valid_[19:0] is a 1. The values on these buses can be updated at any time and are intended to be used as increment values for sync header error counters.

stat_rx_framing_err_1

2

O

RX sync header bits framing error for lane 1.

stat_rx_framing_err_2

2

O

RX sync header bits framing error for lane 2.

stat_rx_framing_err_3

2

O

RX sync header bits framing error for lane 3.

stat_rx_framing_err_4

2

O

RX sync header bits framing error for lane 4.

stat_rx_framing_err_5

2

O

RX sync header bits framing error for lane 5.

stat_rx_framing_err_6

2

O

RX sync header bits framing error for lane 6.

stat_rx_framing_err_7

2

O

RX sync header bits framing error for lane 7.

stat_rx_framing_err_8

2

O

RX sync header bits framing error for lane 8.

stat_rx_framing_err_9

2

O

RX sync header bits framing error for lane 9.

stat_rx_framing_err_10

2

O

RX sync header bits framing error for lane 10.

stat_rx_framing_err_11

2

O

RX sync header bits framing error for lane 11.

stat_rx_framing_err_12

2

O

RX sync header bits framing error for lane 12.

stat_rx_framing_err_13

2

O

RX sync header bits framing error for lane 13.

stat_rx_framing_err_14

2

O

RX sync header bits framing error for lane 14.

stat_rx_framing_err_15

2

O

RX sync header bits framing error for lane 15.

stat_rx_framing_err_16

2

O

RX sync header bits framing error for lane 16.

stat_rx_framing_err_17

2

O

RX sync header bits framing error for lane 17.

stat_rx_framing_err_18

2

O

RX sync header bits framing error for lane 18.

stat_rx_framing_err_19

2

O

RX sync header bits framing error for lane 19.

stat_rx_framing_err_valid_0

1

O

Valid indicator for stat_rx_framing_err_0[1:0]. When this output is sampled as a 1, the value on the corresponding stat_rx_framing_err_0[1:0] is valid.

stat_rx_framing_err_valid_1

1

O

Valid indicator for stat_rx_framing_err_1[1:0].

stat_rx_framing_err_valid_2

1

O

Valid indicator for stat_rx_framing_err_2[1:0].

stat_rx_framing_err_valid_3

1

O

Valid indicator for stat_rx_framing_err_3[1:0].

stat_rx_framing_err_valid_4

1

O

Valid indicator for stat_rx_framing_err_4[1:0].

stat_rx_framing_err_valid_5

1

O

Valid indicator for stat_rx_framing_err_5[1:0].

stat_rx_framing_err_valid_6

1

O

Valid indicator for stat_rx_framing_err_6[1:0].

stat_rx_framing_err_valid_7

1

O

Valid indicator for stat_rx_framing_err_7[1:0].

stat_rx_framing_err_valid_8

1

O

Valid indicator for stat_rx_framing_err_8[1:0].

stat_rx_framing_err_valid_9

1

O

Valid indicator for stat_rx_framing_err_9[1:0].

stat_rx_framing_err_valid_10

1

O

Valid indicator for stat_rx_framing_err_10[1:0].

stat_rx_framing_err_valid_11

1

O

Valid indicator for stat_rx_framing_err_11[1:0].

stat_rx_framing_err_valid_12

1

O

Valid indicator for stat_rx_framing_err_12[1:0].

stat_rx_framing_err_valid_13

1

O

Valid indicator for stat_rx_framing_err_13[1:0].

stat_rx_framing_err_valid_14

1

O

Valid indicator for stat_rx_framing_err_14[1:0].

stat_rx_framing_err_valid_15

1

O

Valid indicator for stat_rx_framing_err_15[1:0].

stat_rx_framing_err_valid_16

1

O

Valid indicator for stat_rx_framing_err_16[1:0].

stat_rx_framing_err_valid_17

1

O

Valid indicator for stat_rx_framing_err_17[1:0].

stat_rx_framing_err_valid_18

1

O

Valid indicator for stat_rx_framing_err_18[1:0].

stat_rx_framing_err_valid_19

1

O

Valid indicator for stat_rx_framing_err_19[1:0].

stat_rx_local_fault

1

O

This output is High when stat_rx_internal_local_fault or stat_rx_received_local_fault is asserted. This output is level sensitive.

stat_rx_synced

20

O

Word Boundary Synchronized. These signals indicate whether a PCS lane is word boundary synchronized. A value of 1 indicates the corresponding PCS lane has achieved word boundary synchronization and it has received a PCS lane marker. This output is level sensitive.

stat_rx_synced_err

20

O

Word Boundary Synchronization Error. These signals indicate whether an error occurred during word boundary synchronization in the respective PCS lane. A value of 1 indicates that the corresponding PCS lane lost word boundary synchronization due to sync header framing bits errors or that a PCS lane marker was never received. This output is level sensitive.

stat_rx_mf_len_err

20

O

PCS Lane Marker Length Error. These signals indicate whether a PCS Lane Marker length mismatch occurred in the respective lane (that is, PCS Lane Markers were received not every CTL_RX_VL_LENGTH_MINUS1 words apart). A value of 1 indicates that the corresponding lane is receiving PCS Lane Markers at wrong intervals. This output remains High until the error condition is removed.

stat_rx_mf_repeat_err

20

O

PCS Lane Marker Consecutive Error. These signals indicate whether four consecutive PCS Lane Marker errors occurred in the respective lane. A value of 1 indicates an error in the corresponding lane. This output remains High until the error condition is removed.

stat_rx_mf_err

20

O

PCS Lane Marker Word Error. These signals indicate that an incorrectly formed PCS Lane Marker Word was detected in the respective lane. A value of 1 indicates an error occurred. This output is pulsed for one clock cycle to indicate the error condition. Pulses can occur in back-to-back cycles.

stat_rx_aligned

1

O

All PCS Lanes Aligned/De-Skewed. This signal indicates whether or not all PCS lanes are aligned and de-skewed. A value of 1 indicates all PCS lanes are aligned and de-skewed. When this signal is a 1, the RX path is aligned and can receive packet data. When this signal is 0, a local fault condition exists. This output is level sensitive.

stat_rx_status

1

O

PCS status. A value of 1 indicates that the PCS is aligned and not in HI_BER state. This output is level sensitive.

stat_rx_block_lock

20

O

Block lock status for each PCS lane. A value of 1 indicates that the corresponding lane has achieved block lock as defined in Clause 82. This output is level sensitive.

stat_rx_aligned_err

1

O

Loss of Lane Alignment/De-Skew. This signal indicates that an error occurred during PCS lane alignment or PCS lane alignment was lost. A value of 1 indicates an error occurred. This output is level sensitive.

stat_rx_misaligned

1

O

Alignment Error. This signal indicates that the lane aligner did not receive the expected PCS lane marker across all lanes. This signal is not asserted until the PCS lane marker has been received at least once across all lanes and at least one incorrect lane marker has been received. This occurs one meta-frame after the error. This signal is not asserted if the lane markers have never been received correctly. Lane marker errors are indicated by the corresponding stat_rx_mf_err signal.

This output is pulsed for one clock cycle to indicate an error condition. Pulses can occur in back-to-back cycles.

stat_rx_remote_fault

1

O

Remote fault indication status. If this bit is sampled as a 1, it indicates a remote fault condition was detected. If this bit is sampled as a 0, a remote fault condition exist does not exist. This output is level sensitive.

stat_rx_pcsl_number_0

5

O

The signal stat_rx_pcsl_number_0[4:0] indicates PCS lane is received on physical lane 0. There are a total of 20 separate stat_rx_pcsl_number[4:0] buses. This bus is only valid when the corresponding bit of be stat_rx_synced[19:0] is a 1. These outputs are level sensitive.

stat_rx_pcsl_number_1

5

O

This signal indicates which PCS lane is received on physical lane 1.

stat_rx_pcsl_number_2

5

O

This signal indicates which PCS lane is received on physical lane 2.

stat_rx_pcsl_number_3

5

O

This signal indicates which PCS lane is received on physical lane 3.

stat_rx_pcsl_number_4

5

O

This signal indicates which PCS lane is received on physical lane 4.

stat_rx_pcsl_number_5

5

O

This signal indicates which PCS lane is received on physical lane 5.

stat_rx_pcsl_number_6

5

O

This signal indicates which PCS lane is received on physical lane 6.

stat_rx_pcsl_number_7

5

O

This signal indicates which PCS lane is received on physical lane 7.

stat_rx_pcsl_number_8

5

O

This signal indicates which PCS lane is received on physical lane 8.

stat_rx_pcsl_number_9

5

O

This signal indicates which PCS lane is received on physical lane 9.

stat_rx_pcsl_number_10

5

O

This signal indicates which PCS lane is received on physical lane 10.

stat_rx_pcsl_number_11

5

O

This signal indicates which PCS lane is received on physical lane 11.

stat_rx_pcsl_number_12

5

O

This signal indicates which PCS lane is received on physical lane 12.

stat_rx_pcsl_number_13

5

O

This signal indicates which PCS lane is received on physical lane 13.

stat_rx_pcsl_number_14

5

O

This signal indicates which PCS lane is received on physical lane 14.

stat_rx_pcsl_number_15

5

O

This signal indicates which PCS lane is received on physical lane 15.

stat_rx_pcsl_number_16

5

O

This signal indicates which PCS lane is received on physical lane 16.

stat_rx_pcsl_number_17

5

O

This signal indicates which PCS lane is received on physical lane 17.

stat_rx_pcsl_number_18

5

O

This signal indicates which PCS lane is received on physical lane 18.

stat_rx_pcsl_number_19

5

O

This signal indicates which PCS lane is received on physical lane 19.

stat_rx_pcsl_demuxed

20

O

PCS Lane Marker found. If a signal of this bus is sampled as 1, it indicates that the receiver has properly de-multiplexed that PCS lane. These outputs are level sensitive.

stat_rx_bad_fcs

3

O

Bad FCS indicator. A value of 1 indicates a packet was received with a bad FCS, but not a stomped FCS. A stomped FCS is defined as the bitwise inverse of the expected good FCS. This output is pulsed for one clock cycle to indicate an error condition. Pulses can occur in back-to-back cycles.

stat_rx_stomped_fcs

3

O

Stomped FCS indicator. A value of 1 or greater indicates that one or more packets were received with a stomped FCS. A stomped FCS is defined as the bitwise inverse of the expected good FCS. This output is pulsed for one clock cycle to indicate the stomped condition. Pulses can occur in back-to-back cycles.

stat_rx_truncated

1

O

Packet truncation indicator. A value of 1 indicates that the current packet in flight is truncated due to its length exceeding ctl_rx_max_packet_len[14:0]. This output is pulsed for one clock cycle to indicate the truncated condition. Pulses can occur in back-to-back cycles.

stat_rx_internal_local_fault

1

O

This signal goes High when an internal local fault is generated due to any one of the following: test pattern generation, bad lane alignment, or high bit error rate. This signal remains High as long as the fault condition persists.

stat_rx_received_local_fault

1

O

This signal goes High when enough local fault words are received from the link partner to trigger a fault condition as specified by the IEEE fault state machine.

This signal remains High as long as the fault condition persists.

stat_rx_bip_err_0

1

O

BIP8 error indicator for PCS lane 0. A non-zero value indicates the BIP8 signature byte was in error for the corresponding PCS lane. A non-zero value is pulsed for one clock cycle. This output is pulsed for one clock cycle to indicate an error condition. Pulses can occur in back-to-back cycles.

stat_rx_bip_err_1

1

O

BIP8 error indicator for PCS lane 1.

stat_rx_bip_err_2

1

O

BIP8 error indicator for PCS lane 2.

stat_rx_bip_err_3

1

O

BIP8 error indicator for PCS lane 3.

stat_rx_bip_err_4

1

O

BIP8 error indicator for PCS lane 4.

stat_rx_bip_err_5

1

O

BIP8 error indicator for PCS lane 5.

stat_rx_bip_err_6

1

O

BIP8 error indicator for PCS lane 6.

stat_rx_bip_err_7

1

O

BIP8 error indicator for PCS lane 7.

stat_rx_bip_err_8

1

O

BIP8 error indicator for PCS lane 8.

stat_rx_bip_err_9

1

O

BIP8 error indicator for PCS lane 9.

stat_rx_bip_err_10

1

O

BIP8 error indicator for PCS lane 10.

stat_rx_bip_err_11

1

O

BIP8 error indicator for PCS lane 11.

stat_rx_bip_err_12

1

O

BIP8 error indicator for PCS lane 12.

stat_rx_bip_err_13

1

O

BIP8 error indicator for PCS lane 13.

stat_rx_bip_err_14

1

O

BIP8 error indicator for PCS lane 14.

stat_rx_bip_err_15

1

O

BIP8 error indicator for PCS lane 15.

stat_rx_bip_err_16

1

O

BIP8 error indicator for PCS lane 16.

stat_rx_bip_err_17

1

O

BIP8 error indicator for PCS lane 17.

stat_rx_bip_err_18

1

O

BIP8 error indicator for PCS lane 18.

stat_rx_bip_err_19

1

O

BIP8 error indicator for PCS lane 19.

stat_rx_hi_ber

1

O

High Bit Error Rate (BER indicator). When set to 1, the BER is too high as defined by the 802.3. This output is level sensitive.

stat_rx_got_signal_os

1

O

Signal Ordered Sets (OS) indication. If this bit is sampled as a 1, it indicates that a Signal OS word was received. Signal OS should not be received in an Ethernet network.

ctl_rx_test_pattern

1

I

Test pattern checking enable for the RX core. A value of 1 enables test mode as defined in Clause 82.2.18. Corresponds to MDIO register bit 3.42.2 as defined in Clause 82.3. Checks for scrambled idle pattern.

ctl_tx_test_pattern

1

I

Test pattern generation enable for the TX core. A value of 1 enables test mode as defined in Clause 82.2.18. Corresponds to MDIO register bit 3.42.3 as defined in Clause 82.3. Generates a scrambled idle pattern.

stat_rx_test_pattern_mismatch

3

O

Test pattern mismatch increment. A non-zero value in any cycle indicates how many mismatches occurred for the test pattern in the RX core. This output is only active when ctl_rx_test_pattern is set to a 1. This output can be used to generate MDIO register 3.43.15:0 as defined in Clause 82.3. This output is pulsed for one clock cycle.

ctl_caui4_mode

1

I

When this input is High, the dedicated 100G Ethernet IP core operates in CAUI-4 mode and when Low in CAUI-10 mode.

This port is available for Runtime Switchable case only.

ctl_tx_lane0_vlm_bip7_override

1

I

When this input is High, the bip7 byte of the PCS lane0 marker is over-ridden by ctl_tx_lane0_vlm_bip7_override_value[7:0]

ctl_tx_lane0_vlm_bip7_override_value

8

I

This input is the override value of the bip7 byte of PCS lane0 marker when ctl_tx_lane0_vlm_bip7_override is asserted.

stat_rx_lane0_vlm_bip7

8

O

This output is the received value of the bip7 byte in the PCS lane0 marker.

stat_rx_lane0_vlm_bip7_valid

1

O

This output, when asserted, indicates that the value of stat_rx_lane0_vlm_bip7[7:0] is valid.

stat_rx_total_bytes

7

O

Increment for the total number of bytes received.

stat_rx_total_packets

3

I

Increment for the total number of packets received.

stat_rx_total_good_bytes

14

O

Increment for the total number of good bytes received. This value is only non-zero when a packet is received completely and contains no errors.

stat_rx_total_good_packets

1

O

Increment for the total number of good packets received. This value is only non-zero when a packet is received completely and contains no errors.

stat_rx_packet_bad_fcs

1

O

Increment for packets between 64 and ctl_rx_max_packet_len bytes that have FCS errors.

stat_rx_packet_64_bytes

1

O

Increment for good and bad packets received that contain 64 bytes.

stat_rx_packet_65_127_bytes

1

O

Increment for good and bad packets received that contain 65 to 127 bytes.

stat_rx_packet_128_255_bytes

1

O

Increment for good and bad packets received that contain 128 to 255 bytes.

stat_rx_packet_256_511_bytes

1

O

Increment for good and bad packets received that contain 256 to 511 bytes.

stat_rx_packet_512_1023_bytes

1

O

Increment for good and bad packets received that contain 512 to 1,023 bytes.

stat_rx_packet_1024_1518_bytes

1

O

Increment for good and bad packets received that contain 1,024 to 1,518 bytes.

stat_rx_packet_1519_1522_bytes

1

O

Increment for good and bad packets received that contain 1,519 to 1,522 bytes.

stat_rx_packet_1523_1548_bytes

1

O

Increment for good and bad packets received that contain 1,523 to 1,548 bytes.

stat_rx_packet_1549_2047_bytes

1

O

Increment for good and bad packets received that contain 1,549 to 2,047 bytes.

stat_rx_packet_2048_4095_bytes

1

O

Increment for good and bad packets received that contain 2,048 to 4,095 bytes.

stat_rx_packet_4096_8191_bytes

1

O

Increment for good and bad packets received that contain 4,096 to 8,191 bytes.

stat_rx_packet_8192_9215_bytes

1

O

Increment for good and bad packets received that contain 8,192 to 9,215 bytes.

stat_rx_packet_small

3

O

Increment for all packets that are less than 64 bytes long.

stat_rx_packet_large

1

O

Increment for all packets that are more than 9,215 bytes long.

stat_rx_unicast

1

O

Increment for good unicast packets.

stat_rx_multicast

1

O

Increment for good multicast packets.

stat_rx_broadcast

1

O

Increment for good broadcast packets.

stat_rx_oversize

1

O

Increment for packets longer than ctl_rx_max_packet_len with good FCS.

stat_rx_toolong

1

O

Increment for packets longer than ctl_rx_max_packet_len with good and bad FCS.

stat_rx_undersize

3

O

Increment for packets shorter than stat_rx_min_packet_len with good FCS.

stat_rx_fragment

3

O

Increment for packets shorter than stat_rx_min_packet_len with bad FCS.

stat_rx_vlan

1

O

Increment for good 802.1Q tagged VLAN packets.

stat_rx_inrangeerr

1

O

Increment for packets with Length field error but with good FCS.

stat_rx_jabber

1

O

Increment for packets longer than ctl_rx_max_packet_len with bad FCS.

stat_rx_pause

1

O

Increment for 802.3x Ethernet MAC Pause packet with good FCS.

stat_rx_user_pause

1

O

Increment for priority based pause packets with good FCS.

stat_rx_bad_code

3

O

Increment for 64B/66B code violations. This signal indicates that the RX PCS receive state machine is in the RX_E state as specified by the 802.3 specifications. This output can be used to generate MDIO register 3.33:7:0 as defined in Clause 82.3.

stat_rx_bad_sfd

1

O

Increment bad SFD. This signal indicates if the Ethernet packet received was preceded by a valid start of frame delimiter (SFD). A value of 1 indicates that an invalid SFD was received.

stat_rx_bad_preamble

1

O

Increment bad preamble. This signal indicates if the Ethernet packet received was preceded by a valid preamble. A value of 1 indicates that an invalid preamble was received.

stat_tx_total_bytes

6

O

Increment for the total number of bytes transmitted.

stat_tx_total_packets

1

O

Increment for the total number of packets transmitted.

stat_tx_total_good_bytes

14

O

Increment for the total number of good bytes transmitted. This value is only non-zero when a packet is transmitted completely and contains no errors.

stat_tx_total_good_packets

1

O

Increment for the total number of good packets transmitted.

stat_tx_bad_fcs

1

O

Increment for packets greater than 64 bytes that have FCS errors.

stat_tx_packet_64_bytes

1

O

Increment for good and bad packets transmitted that contain 64 bytes.

stat_tx_packet_65_127_bytes

1

O

Increment for good and bad packets transmitted that contain 65 to 127 bytes.

stat_tx_packet_128_255_bytes

1

O

Increment for good and bad packets transmitted that contain 128 to 255 bytes.

stat_tx_packet_256_511_bytes

1

O

Increment for good and bad packets transmitted that contain 256 to 511 bytes.

stat_tx_packet_512_1023_bytes

1

O

Increment for good and bad packets transmitted that contain 512 to 1,023 bytes.

stat_tx_packet_1024_1518_bytes

1

O

Increment for good and bad packets transmitted that contain 1,024 to 1,518 bytes.

stat_tx_packet_1519_1522_bytes

1

O

Increment for good and bad packets transmitted that contain 1,519 to 1,522 bytes.

stat_tx_packet_1523_1548_bytes

1

O

Increment for good and bad packets transmitted that contain 1,523 to 1,548 bytes.

stat_tx_packet_1549_2047_bytes

1

O

Increment for good and bad packets transmitted that contain 1,549 to 2,047 bytes.

stat_tx_packet_2048_4095_bytes

1

O

Increment for good and bad packets transmitted that contain 2,048 to 4,095 bytes.

stat_tx_packet_4096_8191_bytes

1

O

Increment for good and bad packets transmitted that contain 4,096 to 8,191 bytes.

stat_tx_packet_8192_9215_bytes

1

O

Increment for good and bad packets transmitted that contain 8,192 to 9,215 bytes.

stat_tx_packet_small

1

O

Increment for all packets that are less than 64 bytes long. Packet transfers of less than 64 bytes are not permitted.

stat_tx_packet_large

1

O

Increment for all packets that are more than 9,215 bytes long.

stat_tx_unicast

1

O

Increment for good unicast packets.

stat_tx_multicast

1

O

Increment for good multicast packets.

stat_tx_broadcast

1

O

Increment for good broadcast packets.

stat_tx_vlan

1

O

Increment for good 802.1Q tagged VLAN packets.

stat_tx_pause

1

O

Increment for 802.3x Ethernet MAC Pause packet with good FCS.

stat_tx_user_pause

1

O

Increment for priority based pause packets with good FCS.

stat_tx_frame_error

1

O

Increment for packets with tx_errin set to indicate an EOP abort.

ctl_rx_pause_enable

9

I

RX pause enable signal. This input is used to enable the processing of the pause quanta for the corresponding priority.

This signal only affects the RX user interface, not the pause processing logic.

ctl_tx_pause_enable

9

I

TX pause enable signal. This input is used to enable the processing of the pause quanta for the corresponding priority. This signal gates transmission of pause packets.

ctl_rx_enable_gcp

1

I

A value of 1 enables global control packet processing.

ctl_rx_check_mcast_gcp

1

I

A value of 1 enables global control multicast destination address processing.

ctl_rx_check_ucast_gcp

1

I

A value of 1 enables global control unicast destination address processing.

ctl_rx_check_sa_gcp

1

I

A value of 1 enables global control source address processing.

ctl_rx_check_etype_gcp

1

I

A value of 1 enables global control Ethertype processing.

ctl_rx_check_opcode_gcp

1

I

A value of 1 enables global control opcode processing.

ctl_rx_enable_pcp

1

I

A value of 1 enables priority control packet processing.

ctl_rx_check_mcast_pcp

1

I

A value of 1 enables priority control multicast destination address processing.

ctl_rx_check_ucast_pcp

1

I

A value of 1 enables priority control unicast destination address processing.

ctl_rx_check_sa_pcp

1

I

A value of 1 enables priority control source address processing.

ctl_rx_check_etype_pcp

1

I

A value of 1 enables priority control Ethertype processing.

ctl_rx_check_opcode_pcp

1

I

A value of 1 enables priority control opcode processing.

ctl_rx_enable_gpp

1

I

A value of 1 enables global pause packet processing.

ctl_rx_check_mcast_gpp

1

I

A value of 1 enables global pause multicast destination address processing.

ctl_rx_check_ucast_gpp

1

I

A value of 1 enables global pause unicast destination address processing.

ctl_rx_check_sa_gpp

1

I

A value of 1 enables global pause source address processing.

ctl_rx_check_etype_gpp

1

I

A value of 1 enables global pause Ethertype processing.

ctl_rx_check_opcode_gpp

1

I

A value of 1 enables global pause opcode processing.

ctl_rx_enable_ppp

1

I

A value of 1 enables priority pause packet processing.

ctl_rx_check_mcast_ppp

1

I

A value of 1 enables priority pause multicast destination address processing.

ctl_rx_check_ucast_ppp

1

I

A value of 1 enables priority pause unicast destination address processing.

ctl_rx_check_sa_ppp

1

I

A value of 1 enables priority pause source address processing.

ctl_rx_check_etype_ppp

1

I

A value of 1 enables priority pause Ethertype processing.

ctl_rx_check_opcode_ppp

1

I

A value of 1 enables priority pause opcode processing.

stat_rx_pause_req

9

O

Pause request signal. When the RX receives a valid pause frame, it sets the corresponding bit of this bus to a 1 and holds at 1 until the pause packet has been processed.

ctl_rx_pause_ack

9

I

Pause acknowledge signal. This bus is used to acknowledge the receipt of the pause frame from the user logic.

stat_rx_pause_valid

9

O

This bus indicates that a pause packet was received and the associated quanta on the stat_rx_pause_quanta[8:0][15:0] bus is valid and must be used for pause processing. If an 802.3x Ethernet MAC Pause packet is received, bit[8] is set to 1.

stat_rx_pause_quanta0

16

O

This bus indicates the quanta received for priority 0 in priority based pause operation. If an 802.3x Ethernet MAC Pause packet is received, the quanta is placed in stat_rx_pause_quanta8[15:0].

stat_rx_pause_quanta1

16

O

This bus indicates the quanta received for priority 1 in a priority based pause operation.

stat_rx_pause_quanta2

16

O

This bus indicates the quanta received for priority 2 in a priority based pause operation.

stat_rx_pause_quanta3

16

O

This bus indicates the quanta received for priority 3 in a priority based pause operation.

stat_rx_pause_quanta4

16

O

This bus indicates the quanta received for priority 4 in a priority based pause operation.

stat_rx_pause_quanta5

16

O

This bus indicates the quanta received for priority 5 in a priority based pause operation.

stat_rx_pause_quanta6

16

O

This bus indicates the quanta received for priority 6 in a priority based pause operation.

stat_rx_pause_quanta7

16

O

This bus indicates the quanta received for priority 7 in a priority based pause operation.

stat_rx_pause_quanta8

16

O

This bus indicates the quanta received for priority 8 in a priority based pause operation.

ctl_tx_pause_req

9

I

If a bit of this bus is set to 1, the dedicated 100G Ethernet IP core transmits a pause packet using the associated quanta value on the ctl_tx_pause_quanta[8:0][15:0] bus. If bit[8] is set to 1, a global pause packet is transmitted. All other bits cause a priority pause packet to be transmitted. Each bit of this bus must be held at a steady state for a minimum of 16 cycles before the next transition.

ctl_tx_pause_quanta0

16

I

This bus indicates the quanta to be transmitted for priority 0 in a priority based pause operation. If an 802.3x Ethernet MAC Pause packet is to be transmitted, the quanta is placed in ctl_tx_pause_quanta8[15:0].

ctl_tx_pause_quanta1

16

I

This bus indicates the quanta to be transmitted for priority 1 in a priority based pause operation.

ctl_tx_pause_quanta2

16

I

This bus indicates the quanta to be transmitted for priority 2 in a priority based pause operation.

ctl_tx_pause_quanta3

16

I

This bus indicates the quanta to be transmitted for priority 3 in a priority based pause operation.

ctl_tx_pause_quanta4

16

I

This bus indicates the quanta to be transmitted for priority 4 in a priority based pause operation.

ctl_tx_pause_quanta5

16

I

This bus indicates the quanta to be transmitted for priority 5 in a priority based pause operation.

ctl_tx_pause_quanta6

16

I

This bus indicates the quanta to be transmitted for priority 6 in a priority based pause operation.

ctl_tx_pause_quanta7

16

I

This bus indicates the quanta to be transmitted for priority 7 in a priority based pause operation.

ctl_tx_pause_quanta8

16

I

This bus indicates the quanta to be transmitted for priority 8 in a priority based pause operation.

ctl_tx_pause_refresh_timer0

16

I

This bus sets the retransmission time of pause packets for priority 0 in a priority based pause operation.

ctl_tx_pause_refresh_timer1

16

I

This bus sets the retransmission time of pause packets for priority 1 in a priority based pause operation.

ctl_tx_pause_refresh_timer2

16

I

This bus sets the retransmission time of pause packets for priority 2 in a priority based pause operation.

ctl_tx_pause_refresh_timer3

16

I

This bus sets the retransmission time of pause packets for priority 3 in a priority based pause operation.

ctl_tx_pause_refresh_timer4

16

I

This bus sets the retransmission time of pause packets for priority 4 in a priority based pause operation.

ctl_tx_pause_refresh_timer5

16

I

This bus sets the retransmission time of pause packets for priority 5 in a priority based pause operation.

ctl_tx_pause_refresh_timer6

16

I

This bus sets the retransmission time of pause packets for priority 6 in a priority based pause operation.

ctl_tx_pause_refresh_timer7

16

I

This bus sets the retransmission time of pause packets for priority 7 in a priority based pause operation.

ctl_tx_pause_refresh_timer8

16

I

This bus sets the retransmission time of pause packets for global pause operation.

ctl_tx_resend_pause

1

I

Re-transmit pending pause packets. When this input is sampled as 1, all pending pause packets are retransmitted as soon as possible (that is, after the current packet in flight is completed) and the retransmit counters are reset. This input should be pulsed to 1 for one cycle at a time.

stat_tx_pause_valid

9

O

If a bit of this bus is set to 1, the dedicated 100G Ethernet IP core has transmitted a pause packet. If bit[8] is set to 1, a global pause packet is transmitted. All other bits cause a priority pause packet to be transmitted.

ctl_tx_systemtimerin

80

I

System timer input for the TX. In normal clock mode, the time format is according to the IEEE 1588 format, with 48 bits for seconds and 32 bits for nanoseconds. In transparent clock mode, bit 63 represents the sign bit, bits 62:16 carry nanoseconds, and bits 15:0 carry fractional nanoseconds. Refer to the IEEE 1588v2 for the representational definitions. This input must be in the TX clock domain.

tx_ptp_tstamp_valid_out

1

O

This bit indicates that a valid timestamp is being presented on the TX.

tx_ptp_pcslane_out

5

O

This bus identifies which of the 20 PCS lanes that the SOP was detected on for the corresponding timestamp.

tx_ptp_tstamp_tag_out

16

O

Tag output corresponding to tx_ptp_tag_field_in[15:0].

tx_ptp_tstamp_out

80

O

Time stamp for the transmitted packet SOP corresponding to the time at which it passed the capture plane. The representation of the bits contained in this bus is the same as the timer input.

tx_ptp_1588op_in

2

I

2’b00 – “No operation”: no timestamp will be taken and the frame will not be modified.

2’b01 – “1-step”: a timestamp should be taken and

inserted into the frame.

2’b10 – “2-step”: a timestamp should be taken and

returned to the client using the additional ports of 2-step operation. The frame itself will not be modified.

2’b11 – Reserved.

Note: The CMAC core samples this signal at SOP.

tx_ptp_tag_field_in

16

I

The usage of this field is dependent on the 1588 operation

For “No operation”, this field will be ignored.

For “1-step” and “2-step”, this field is a tag field. This tag value will be returned to the client with the timestamp for the current frame using the additional ports of 2-step operation. This tag value can be used by software to ensure that the timestamp can be matched with the precise timing protocol (PTP) frame that it sent for transmission.

Note: The CMAC core samples this signal at SOP.

tx_ptp_upd_chksum_in

1

I

The usage of this field is dependent on the 1588 operation.

For “No operation” or “2-step”, this bit will be ignored.

For “1-step”:

° 1’b0: The PTP frame does not contain a UDP checksum.

° 1’b1: The PTP frame does contain a UDP checksum which the core is required to recalculate.

tx_ptp_chksum_offset_in

16

I

The usage of this field is dependent on the “1588 operation” and on the “Update Checksum” bit.

For “No operation”, for “2-step” or for “1-step” when “Update Checksum” is set to 1’b0, this field will be ignored.

For “1-step” when “Update Checksum” is set to 1’b1, this field is a numeric value indicating the number of bytes into the frame to where the first byte of the checksum is located (where a value of 0 represents the first byte of the Destination Address, etc).

Note: The IPv6 header size is unbounded, so this field is able to cope with all frames sizes up to 16K jumbo frames. Only even values are supported.

tx_ptp_tstamp_offset_in

16

I

The usage of this field is dependent on the 1588 operation

For “No operation” or “2-step” this field is ignored.

For “1-step”, this field is a numeric value indicating the number of bytes into the frame to where the first byte of the timestamp to be inserted is located (where a value of 0 represents the first byte of the Destination Address, etc).

This input is also used to specify the offset for the correction field in 1-step Transparent Clock mode.

Note: The IPv6 header size is unbounded, so this field is able to cope with all frames sizes up to 16K jumbo frames.
Only even values are supported.
In transparent clock mode and when tx_ptp_upd_chksum_in=1, this value cannot be greater than tx_ptp_chksum_offset_in + 34 (decimal).

ctl_tx_ptp_vlane_adjust_mode

1

I

When asserted, this signal applies an adjustment to the TX timestamps according to the PCS lane on which the SOP occurs. When zero, no adjustment is made. This signal only has effect for 1-step operation.

stat_tx_ptp_fifo_write_error

1

O

Transmit PTP FIFO write error. A 1 on this status indicates that an error occurred during the PTP Tag write. A TX Path reset is required to clear the error.

stat_tx_ptp_fifo_read_error

1

O

Transmit PTP FIFO read error. A 1 on this status indicates that an error occurred during the PTP Tag read. A TX Path reset is required to clear the error.

ctl_rx_systemtimerin

80

I

System timer input for the RX.

In normal clock mode, the time format is according to the IEEE 1588 format, with 48 bits for seconds and 32 bits for nanoseconds.

In transparent clock mode, bit 63 represents the sign bit, bits 62:16 carry nanoseconds, and bits 15:0 carry fractional nanoseconds. Refer to the IEEE 1588v2 for the representational definitions.

This input must be in the same clock domain as the lane 0 RX SerDes.

rx_ptp_tstamp_out

80

O

Time stamp for the received packet SOP corresponding to the time at which it passed the capture plane. This signal will be valid starting at the same clock cycle during which the SOP is asserted for one of the LBUS segments.

The representation of the bits contained in this bus is the same as the timer input.

rx_ptp_pcslane_out

5

O

This bus identifies which of the 20 PCS lanes that the SOP was detected on for the corresponding timestamp.

This signal will be valid starting at the same clock cycle during which the SOP is asserted for one of the LBUS segments.

rx_lane_aligner_fill_0

7

O

This output indicates the fill level of the alignment buffer for PCS lane0. This information can be used by the PTP application, together with the signal rx_ptp_pcslane_out[4:0], to adjust for the lane skew of the arriving SOP. The units are SerDes clock cycles.

rx_lane_aligner_fill_1

7

O

This output indicates the fill level of the alignment buffer for PCS lane1.

rx_lane_aligner_fill_2

7

O

This output indicates the fill level of the alignment buffer for PCS lane2.

rx_lane_aligner_fill_3

7

O

This output indicates the fill level of the alignment buffer for PCS lane3.

rx_lane_aligner_fill_4

7

O

This output indicates the fill level of the alignment buffer for PCS lane4.

rx_lane_aligner_fill_5

7

O

This output indicates the fill level of the alignment buffer for PCS lane5.

rx_lane_aligner_fill_6

7

O

This output indicates the fill level of the alignment buffer for PCS lane6.

rx_lane_aligner_fill_7

7

O

This output indicates the fill level of the alignment buffer for PCS lane7.

rx_lane_aligner_fill_8

7

O

This output indicates the fill level of the alignment buffer for PCS lane8.

rx_lane_aligner_fill_9

7

O

This output indicates the fill level of the alignment buffer for PCS lane9.

rx_lane_aligner_fill_10

7

O

This output indicates the fill level of the alignment buffer for PCS lane10.

rx_lane_aligner_fill_11

7

O

This output indicates the fill level of the alignment buffer for PCS lane11.

rx_lane_aligner_fill_12

7

O

This output indicates the fill level of the alignment buffer for PCS lane12.

rx_lane_aligner_fill_13

7

O

This output indicates the fill level of the alignment buffer for PCS lane13.

rx_lane_aligner_fill_14

7

O

This output indicates the fill level of the alignment buffer for PCS lane14.

rx_lane_aligner_fill_15

7

O

This output indicates the fill level of the alignment buffer for PCS lane15.

rx_lane_aligner_fill_16

7

O

This output indicates the fill level of the alignment buffer for PCS lane16.

rx_lane_aligner_fill_17

7

O

This output indicates the fill level of the alignment buffer for PCS lane17.

rx_lane_aligner_fill_18

7

O

This output indicates the fill level of the alignment buffer for PCS lane18.

rx_lane_aligner_fill_19

7

O

This output indicates the fill level of the alignment buffer for PCS lane19.

drp_clk

1

I

DRP interface clock. When DRP is not used, this can be tied to GND.

drp_addr

10

I

DRP address bus.

drp_di

16

I

Data bus for writing configuration data from the FPGA logic resources to the 100G Ethernet IP core.

drp_en

1

I

DRP enable signal.

0: No read or write operations performed.

1: Enables a read or write operation.

For write operations, DRP_WE and DRP_EN should be driven High for one DRP_CLK cycle only.

drp_do

16

O

Data bus for reading configuration data from the 100G Ethernet IP core to the FPGA logic resources.

drp_rdy

1

O

Indicates operation is complete for write operations and data is valid for read operations.

drp_we

1

I

DRP write enable.

0: Read operation when DRP_EN is 1.

1: Write operation when DRP_EN is 1.

For write operations, DRP_WE and DRP_EN should be driven High for one DRP_CLK cycle only.

user_reg0

32

O

User-defined output from the AXI4-Lite register map user_reg0 register.

Note: This input is available when Include AXI4-Lite Control and Statistics Interface is selected in the General Tab.

rx_otn_bip8_{0:OTN_LANES-1}

8

O

Recalculated BIP values for OTN interface.

rx_otn_data_{0:OTN_LANES-1}

66

O

Data output for the receive data path.

[65:64] = sync header

[63:0] = data

rx_otn_ena

1

O

Indicates that the data on the rx_otn_data_* buses are valid.

rx_otn_lane0

1

O

Indicates that the data word for PCS lane 0 is present on rx_otn_data_0.

rx_otn_vlmarker

1

O

Indicates that the data on rx_otn_data_* buses are the alignment marker words.

tx_preamblein

56

I

Custom tx preamble input data.

It should be valid during the start of packet.

rx_preambleout

56

O

RX preamble output data.

ctl_tx_rsfec_enable

1

I

TX control input for RS-FEC core

Note: This port is available when Enable TX OTN Interface option is deselected and Include IEEE 802.3bj RS-FEC option is selected in the General tab.

ctl_rx_rsfec_enable

1

I

RX control input for RS-FEC core.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab.

ctl_rsfec_ieee_error_indication_mode

1

I

IEEE error indication control input for RS-FEC core.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab, or the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

ctl_rx_rsfec_enable_correction

1

I

Error correction control input for RS-FEC core.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab, or the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

ctl_rx_rsfec_enable_indication

1

I

Error indication control input for RS-FEC core.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab, or the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

rsfec_bypass_rx_din

330

I

RX data input for RS-FEC decoder in Transcode Bypass mode.

Note: This port is available when the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

rsfec_bypass_rx_din_cw_start

1

I

RX data input start of codeword for RS-FEC decoder in Transcode Bypass mode.

Note: This port is available when the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

rsfec_bypass_tx_din

330

I

TX data input for RS-FEC encoder in Transcode Bypass mode.

Note: This port is available when the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

rsfec_bypass_tx_din_cw_start

1

I

TX data input start of codeword for RS-FEC encoder in Transcode Bypass mode.

Note: This port is available when the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

rsfec_bypass_rx_dout

330

O

RX data output from the RS-FEC decoder in Transcode Bypass mode.

Note: This port is available when the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

rsfec_bypass_rx_dout_cw_start

1

O

RX data out start of codeword from the RS-FEC decoder in Transcode Bypass mode.

Note: This port is available when the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

rsfec_bypass_rx_dout_valid

1

O

RX data out valid from the RS-FEC decoder in Transcode Bypass mode.

Note: This port is available when the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

rsfec_bypass_tx_dout

330

O

TX data output from the RS-FEC encoder in Transcode Bypass mode.

Note: This port is available when the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

rsfec_bypass_tx_dout_cw_start

1

O

TX data out start of codeword from the RS-FEC encoder in Transcode Bypass mode.

Note: This port is available when the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

rsfec_bypass_tx_dout_valid

1

O

TX data out valid from the RS-FEC encoder in Transcode Bypass mode.

Note: This port is available when the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

stat_rx_rsfec_am_lock0

1

O

RS-FEC RX lane 0 locked and aligned status.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab.

stat_rx_rsfec_am_lock1

1

O

RS-FEC RX lane 1 locked and aligned status

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab.

stat_rx_rsfec_am_lock2

1

O

RS-FEC RX lane 2 locked and aligned status

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab.

stat_rx_rsfec_am_lock3

1

O

RS-FEC RX lane 3 locked and aligned status.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab.

stat_rx_rsfec_corrected_cw_inc

1

O

Indicates when High that the RS decoder in the core successfully corrected an RS-FEC code word.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab, or the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

stat_rx_rsfec_cw_inc

1

O

Indicates when High that the cw_inc flags are valid for each corrected/uncorrected RS-FEC code word.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab, or the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

stat_rx_rsfec_uncorrected_cw_inc

1

O

Indicates when High that the RS decoder in the core failed to correct an RS-FEC code word.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab, or the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

stat_rx_rsfec_err_count0_inc

3

O

Indicates the number of symbol errors detected on lane 0.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab, or the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

stat_rx_rsfec_err_count1_inc

3

O

Indicates the number of symbol errors detected on lane 1.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab.

stat_rx_rsfec_err_count2_inc

3

O

Indicates the number of symbol errors detected on lane 2.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab.

stat_rx_rsfec_err_count3_inc

3

O

Indicates the number of symbol errors detected on lane 3.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab.

stat_rx_rsfec_hi_ser

1

O

Set to 1 if the number of RS-FEC symbol errors in a window of 8,192 codewords exceeds the threshold of K = 417. Pulsed High. There is no latching High behavior on this output. See the 802.3 spec register 1.201.2.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab, or the Enable RS-FEC Transcode Bypass option is selected in the RS-FEC Transcode Bypass tab.

stat_rx_rsfec_lane_alignment_status

1

O

High if the RS-FEC RX lanes are all locked and aligned.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab.

stat_rx_rsfec_lane_fill_0

14

O

Instantaneous delay that has been applied to the SerDes lane 0 in the alignment and deskew block.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab.

stat_rx_rsfec_lane_fill_1

14

O

Instantaneous delay that has been applied to the SerDes lane 1 in the alignment and deskew block.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab.

stat_rx_rsfec_lane_fill_2

14

O

Instantaneous delay that has been applied to the SerDes lane 2 in the alignment and deskew block.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab.

stat_rx_rsfec_lane_fill_3

14

O

Instantaneous delay that has been applied to the SerDes lane 3 in the alignment and deskew block.

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab.

stat_rx_rsfec_lane_mapping

8

O

8 LSBs of the 802.3 spec register 1.206, showing

which PMA lane is mapped to each FEC lane.

Bits [1:0] = FEC lane mapping 0

Bits [3:2] = FEC lane mapping 1

Bits [5:4] = FEC lane mapping 2

Bits [7:6] = FEC lane mapping 3

Note: This port is available when the Include IEEE 802.3bj RS-FEC option is selected in the General tab.

AXI4-Lite interface ports are visible only when you select the Include AXI4-Lite Control and Statistics Interface option from the General Tab . Refer to AXI4 Interface User Logic for the AXI4-Lite port list and descriptions.