Clocking - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

The UltraScale+™ Devices Integrated Block for 100G Ethernet subsystem has up to 13 clock inputs for the CAUI-10 interface and up to seven clock inputs for the CAUI-4 interface. These clocks include the RX_SERDES_CLK[9:0] and RX_SERDES_CLK[3:0] respectively for the CAUI-10 and CAUI-4 modes, TX_CLK , RX_CLK and the DRP_CLK . The DRP_CLK is optional and is necessary only during a DRP operation.

The 10 CAUI-10 or 4 CAUI-4 RX_SERDES_CLK clocks must not have an FPGA induced dynamic skew of more than 1000 ps. More details on the clocks are provided in the following sections.

The Runtime Switchable mode follows the same clocking structure as the one from CAUI-10 described previously.