Common Ports - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

Table: Common Ports lists the RS-FEC ports that are used for control configuration and status reporting in both normal mode and transcode bypass mode.

Table A-1: Common Ports

Name

I/O

Clock

Domain

Description

ctl_rx_rsfec_enable_correction

I

rx_clk

RS-FEC correction enable

ctl_rsfec_ieee_error_indication_mode

I

rx_clk

RS-FEC error indication mode (1=IEEE compliant mode, 0=allow simultaneous correction and indication bypass)

ctl_rx_rsfec_enable_indication

I

rx_clk

RS-FEC indication enable

ctl_rx_rsfec_enable

I

rx_clk

RX RS-FEC enable

ctl_tx_rsfec_enable

I

tx_clk

TX RS-FEC enable

ctl_rsfec_enable_transcoder_bypass_mode

I

Core clock

Transcoder bypass mode enable

stat_rx_rsfec_hi_ser

O

rx_clk

Set to 1 if the number of RS-FEC symbol errors in a window of 8,192 codewords exceeds the threshold of K=417. Pulsed High. There is no latching High behavior on this output. See the 802.3 spec register 1.201.2.

stat_rx_rsfec_am_lock0

O

rx_clk

High if the RS-FEC RX lane 0 is locked and aligned

stat_rx_rsfec_am_lock1

O

rx_clk

High if the RS-FEC RX lane 1 is locked and aligned

stat_rx_rsfec_am_lock2

O

rx_clk

High if the RS-FEC RX lane 2 is locked and aligned

stat_rx_rsfec_am_lock3

O

rx_clk

High if the RS-FEC RX lane 3 is locked and aligned

stat_rx_rsfec_lane_alignment_status

O

rx_clk

High if the RS-FEC RX lanes are all locked and aligned

stat_rx_rsfec_corrected_cw_inc

O

rx_clk

High when the count of corrected RS codewords should be incremented.

stat_rx_rsfec_uncorrected_cw_inc

O

rx_clk

High when the count of uncorrected RS codewords should be incremented.

stat_rx_rsfec_cw_inc

O

rx_clk

High when the total count of received RS codewords should be incremented.

stat_rx_rsfec_lane_mapping[7:0]

O

rx_clk

8 LSBs of the 802.3 spec register 1.206, showing which PMA lane is mapped to each FEC lane.

Bits [1:0] = FEC lane mapping 0

Bits [3:2] = FEC lane mapping 1

Bits [5:4] = FEC lane mapping 2

Bits [7:6] = FEC lane mapping 3

stat_rx_rsfec_err_count0_inc[2:0]

O

rx_clk

Value to increment an external accumulator for the number of RS symbol errors on FEC lane 0.

stat_rx_rsfec_err_count1_inc[2:0]

O

rx_clk

Value to increment an external accumulator for the number of RS symbol errors on FEC lane 1.

stat_rx_rsfec_err_count2_inc[2:0]

O

rx_clk

Value to increment an external accumulator for the number of RS symbol errors on FEC lane 2.

stat_rx_rsfec_err_count3_inc[2:0]

O

rx_clk

Value to increment an external accumulator for the number of RS symbol errors on FEC lane 3.

stat_rx_rsfec_rx_lane_fill_0[12:0]

O

rx_clk

Bits [13:7] give the fill level of the RX lane 0 FIFO. Bits [6:0] give the bit-level shift being applied to lane 0, in units of 1/80 of a clock cycle.

stat_rx_rsfec_rx_lane_fill_1[12:0]

O

rx_clk

Bits [13:7] give the fill level of the RX lane 1 FIFO. Bits [6:0] give the bit-level shift being applied to lane 1 in units of 1/80 of a clock cycle.

stat_rx_rsfec_rx_lane_fill_2[12:0]

O

rx_clk

Bits [13:7] give the fill level of the RX lane 2 FIFO. Bits [6:0] give the bit-level shift being applied to lane 2, in units of 1/80 of a clock cycle.

stat_rx_rsfec_rx_lane_fill_3[12:0]

O

rx_clk

Bits [13:7] give the fill level of the RX lane 3 FIFO. Bits [6:0] give the bit-level shift being applied to lane 3, in units of 1/80 of a clock cycle.