Ethernet Specific Checks - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

Many issues can occur during the first hardware test. This section details the debugging process. It is assumed that the 100G Ethernet IP core has already passed all simulation testing which is being implemented in hardware. This is a pre-requisite for any kind of hardware debug.

The following sequence helps to isolate ethernet-specific problems:

1. Clean up Signal Integrity .

2. Ensure that each SerDes achieves CDR lock.

3. Check that each lane has achieved word alignment.

4. Check that lane alignment has been achieved.

5. Proceed to Interface Debug and Protocol Debug .