Example Design Hierarchy (GT Subcore in Example Design) - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English
Figure 5-2: Example Design Hierarchy (GT Subcore in Example Design)

X-Ref Target - Figure 5-2

X22132-pg203-ex-des-hier-gt-subcore.jpg

This Figure shows the instantiation of various modules and their hierarchy in the example design when the GT (serial transceiver) is outside the IP core, that is, in the example design. This hierarchical example design is delivered when you select the Include GT subcore in example design option from the CMAC/GT Selection and Configuration tab.

The cmac_usplus_0_core_support.v is present in the hierarchy when you select the Include GT subcore in example design option from the CMAC/GT Selection and Configuration tab, or the Include Shared Logic in example design option from the
CMAC/GT Selection and Configuration tab. This instantiates the cmac_usplus_0_shared_logic_wrapper.v module and the cmac_usplus_0.v module for the Include Shared Logic in example design option. The cmac_usplus_0_gt_wrapper.v module is present when you select the GT subcore in example design option.

The cmac_usplus_0 module instantiates the cmac_usplus_0_wrapper module that contains the CMAC and Sync registers along with the pipeline registers to synchronize the data between the CMAC core and the GT subcore (in the example design). The GT subcore generates the required clock frequencies with help of the clocking helper blocks for the CMAC core. The cmac_usplus_0_pkt_gen_mon module instantiates cmac_usplus_0_pkt_gen (packet generator) and cmac_usplus_0_pkt_mon (packet monitor). The cmac_usplus_0_pkt_gen_mon and cmac_usplus_0_core_support handshake with each other using several signals such as GT locked, RX alignment and data transfer signals as per LBUS protocol (described in more detail later). The cmac_usplus_0_pkt_gen module is mainly responsible for the generation of packets. It contains a state machine that monitors the status of GT and CMAC (that is, GT lock and RX alignment) and sends traffic to the core. Similarly the cmac_usplus_0_pkt_mon module is mainly responsible for reception and checking of packets from the core. It also contains a state machine that monitors the status of GT and CMAC (that is, GT lock and RX alignment) and receives traffic from the core.

Other optional modules instantiated in the example design are as follows:

cmac_usplus_0_shared_logic_wrapper : When you select Include GT subcore in example design or Include Shared Logic in example design in the CMAC/GT Selection and Configuration tab of the 100G Ethernet IP Vivado IDE, this module is available in the example design. This wrapper contains three modules: cmac_usplus_0_clocking_wrapper , cmac_usplus_0_reset_wrapper , and cmac_usplus_0_common_wrapper . The cmac_usplus_0_clocking_wrapper has the instantiation of the IBUFDS for the gt_ref_clk , and the cmac_usplus_0_reset_wrapper brings out the reset architecture instantiated between the core and the GT. The cmac_usplus_0_common_wrapper brings the transceiver common module out of the 100G Ethernet IP core.

cmac_usplus_0_gt_wrapper : This module is present in the example design when you select the Include GT subcore in example design option from the CMAC/GT Selection and Configuration tab. This module is having instantiations of the GT along with various helper blocks. The clocking helper blocks are used to generate the required clock frequency for the core.