Feature Enhancements in UltraScale+ Integrated 100G Ethernet IP - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

Added integrated Reed Solomon-Forward Error Correction (RS-FEC) block including the Transcode Bypass mode.

Added support for programmable inter-packet gap (IPG).

Added support for custom preambles.

Added support for overclocking. See the Virtex UltraScale+ Architecture Data Sheet: DC and AC Switching Characteristics Data Sheet [Ref 4] for supported line rates.

° CMAC CAUI-10 10x12.5G in -2 and above.

° CMAC CAUI-4 with RS-FEC 4x31.25G in -3 and above.

Added registers on all the input for better timing.

Added behavioral code for the standard cells for secure IP to help speed up simulation.