The following is a summary of the core features:
• IEEE 1588-2008 [Ref 1] one-step and two-step hardware timestamping with transparent clock and ordinary clock support
• Optional Transmit side OTN interface implemented in the fabric logic
• Dynamic and static deskew support
• 20 PCS lanes (PCSLs) for the 100G Ethernet IP core
• GTY, GTH, or GTM transceivers used for UltraScale+ devices
• PCS Lane marker framing and de-framing including reordering of each PCS lane
• Link status and alignment monitoring reporting
• 64B/66B decoding and encoding as defined in IEEE std 802.3-2012 Clause 82 [Ref 2]
• Scrambling and descrambling using x 58 + x 39 + 1 polynomial
• Inter-Packet gap (IPG) insertion and deletion as required by IEEE std 802.3-2012 Clause 82 [Ref 2]
• Optional frame check sequence (FCS) calculation and addition in the transmit direction
• Programmable inter-packet gap
• Support for custom preambles
• FCS checking and optional FCS removal in the receive direction
• Support for 802.3x and priority-based pause operation
• DRP interface for dynamic reconfiguration of the core
• Detailed statistics gathering
° Total bytes
° Total packets
° Good bytes
° Good packets
° Unicast packets
° Multicast packets
° Broadcast packets
° Pause packets
° Virtual local area network (VLAN) tagged packets
° 64B/66B code violations
° Bad preambles
° Bad FCS
° Packet histogram for varied packet sizes