Features - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID

PG203

Release Date

2022-11-02

Version

3.1 English

• Supports CAUI-10, CAUI-4, 100GAUI-2, 100GAUI-4, and run-time switchable between CAUI-4 and CAUI-10 modes

• 512-bit segmented local bus (LBUS) user interface/AXI4-Stream (AXIS) user interface at ~322 MHz

• 32-bit interface to the serial transceiver for CAUI-10 lanes, 80-bit interface to the serial transceiver for CAUI-4/100GAUI-4 lanes and 160-bit interface to the serial transceiver for 100GAUI-2 lanes

• IEEE 1588-2008 [Ref 1] one-step and two-step hardware timestamping at ingress and egress at full 80 bits

• Pause frame processing including priority based flow control per IEEE std 802.3-2012 Annex 31 [Ref 2]

• Optional fee-based Auto-Negotiation and Link Training feature for CAUI-4 mode

• Optional built-in 802.3bj-2014 Clause 91 RS-FEC block in CAUI-4 and runtime switch CAUI-4 modes

• Receive side OTN interface

• Optional soft TX OTN interface support

LogiCORE IP Facts Table
Core Specifics
Supported Device Family ⁽¹⁾	UltraScale+™
Supported User Interfaces	Segmented LBUS, AXI4-Stream
Resources	Performance and Resource Utilization web page
Provided with Core
Design Files	Verilog
Example Design	Verilog
Test Bench	Verilog
Constraints File	Xilinx Design Constraints (XDC)
Simulation Model	Verilog
Supported S/W Driver	N/A
Tested Design Flows ⁽²⁾
Design Entry	Vivado® Design Suite
Simulation	For supported simulators, see the Xilinx Design Tools: Release Notes Guide .
Synthesis	Vivado synthesis
Support
Release Notes and Known Issues	Master Answer Record: 67395
All Vivado IP Change Logs	Master Vivado IP Change Logs: 72775
Xilinx Support web page
Notes: 1. For a complete list of supported devices, see the Vivado IP catalog. 2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide .