IEEE 1588 Support - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

To support IEEE 1588 timestamping applications, the RS-FEC engine captures the 80-bit system timer which is clocked on the rs_serdes_clk[0] clock domain, and provides appropriate delay and gearbox adjustments in addition to those applied by the Integrated 100G Ethernet block.

IEEE 1588 support is not available in transcode bypass mode.