The Xilinx® UltraScale+™ Devices Integrated 100G Ethernet IP subsystem provides a high-performance, low-latency 100 Gb/s Ethernet port that allows for a wide range of user customization and statistics gathering. The dedicated block provides both the 100G Ethernet MAC, and RS-FEC logic with support for IEEE 1588-2008 [Ref 1] hardware timestamping.
The 100G Ethernet IP core provides the following configurations: (CAUI-10) 10x10.3125G, (CAUI-4) 4x25.78125G, (100GAUI-2) 2x53.125G, and (100GAUI-4) 4x26.5625G. The core is switchable between CAUI-4 and CAUI-10 modes at run time. The 100G Ethernet IP core is designed to the IEEE std 802.3-2012 [Ref 2] specification.