Link Training Signals - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

Table: Link Training Signals describes the additional signals available when the link training feature is present.

Table D-4: Link Training Signals

Name

I/O

Clock Domain

Description

ctl_lt_training_enable

I

tx_serdes_clk

Enables link training. When link training is disabled, all PCS lanes function in mission mode.

ctl_lt_restart_training

I

tx_serdes_clk

This signal triggers a restart of link training regardless of the current state.

ctl_lt_rx_trained[3:0]

I

tx_serdes_clk

This signal is asserted to indicate that the receiver finite impulse response (FIR) filter coefficients have all been set, and that the receiver portion of training is complete.

ctl_lt_preset_to_tx[3:0]

I

tx_serdes_clk

This signal is used to set the value of the preset bit that is transmitted to the link partner in the control block of the training frame.

ctl_lt_initialize_to_tx[3:0]

I

tx_serdes_clk

This signal is used to set the value of the initialize bit that is transmitted to the link partner in the control block of the training frame.

ctl_lt_pseudo_seed0[10:0]

ctl_lt_pseudo_seed1[10:0]

ctl_lt_pseudo_seed2[10:0]

ctl_lt_pseudo_seed3[10:0]

I

tx_serdes_clk

This 11-bit signal seeds the training pattern generator.

ctl_lt_k_p1_to_tx0[1:0]

ctl_lt_k_p1_to_tx1[1:0]

ctl_lt_k_p1_to_tx2[1:0]

ctl_lt_k_p1_to_tx3[1:0]

I

tx_serdes_clk

This 2-bit field is used to set the value of the k+1 coefficient update field that is transmitted to the link partner in the control block of the training frame.

ctl_lt_k0_to_tx0[1:0]

ctl_lt_k0_to_tx1[1:0]

ctl_lt_k0_to_tx2[1:0]

ctl_lt_k0_to_tx3[1:0]

I

tx_serdes_clk

This 2-bit field is used to set the value of the k0 coefficient update field that is transmitted to the link partner in the control block of the training frame.

ctl_lt_k_m1_to_tx0[1:0]

ctl_lt_k_m1_to_tx1[1:0]

ctl_lt_k_m1_to_tx2[1:0]

ctl_lt_k_m1_to_tx3[1:0]

I

tx_serdes_clk

This 2-bit field is used to set the value of the k-1 coefficient update field that is transmitted to the link partner in the control block of the training frame.

ctl_lt_stat_p1_to_tx0[1:0]

ctl_lt_stat_p1_to_tx1[1:0]

ctl_lt_stat_p1_to_tx2[1:0]

ctl_lt_stat_p1_to_tx3[1:0]

I

tx_serdes_clk

This 2-bit field is used to set the value of the k+1 coefficient update status that is transmitted to the link partner in the status block of the training frame.

ctl_lt_stat0_to_tx0[1:0]

ctl_lt_stat0_to_tx1[1:0]

ctl_lt_stat0_to_tx2[1:0]

ctl_lt_stat0_to_tx3[1:0]

I

tx_serdes_clk

This 2-bit field is used to set the value of the k0 coefficient update status that is transmitted to the link partner in the status block of the training frame.

ctl_lt_stat_m1_to_tx0[1:0]

ctl_lt_stat_m1_to_tx1[1:0]

ctl_lt_stat_m1_to_tx2[1:0]

ctl_lt_stat_m1_to_tx3[1:0]

I

tx_serdes_clk

This 2-bit field is used to set the value of the k-1 coefficient update status that is transmitted to the link partner in the status block of the training frame.

stat_lt_signal_detect[3:0]

O

rx_serdes_clk

This signal indicates when the

respective link training state machine has entered the SEND_DATA state, in which normal PCS operation can resume.

stat_lt_training[3:0]

O

rx_serdes_clk

This signal indicates when the respective link training state machine is performing link training.

stat_lt_training_fail[3:0]

O

rx_serdes_clk

This signal is asserted during link training if the corresponding link training state machine detects a time-out during the training period.

stat_lt_rx_sof[3:0]

O

rx_serdes_clk

This output is High for 1 RX SerDes clock cycle to indicate the start of the link training frame.

stat_lt_frame_lock[3:0]

O

rx_serdes_clk

When link training has begun, these signals are asserted, for each physical medium dependent (PMD) lane, when the corresponding link training receiver is able to establish a frame synchronization with the link partner.

stat_lt_preset_from_rx[3:0]

O

rx_serdes_clk

This signal reflects the value of the preset control bit received in the control block from the link partner.

stat_lt_initialize_from_rx[3:0]

O

rx_serdes_clk

This signal reflects the value of the initialize control bit received in the control block from the link partner.

stat_lt_k_p1_from_rx0[1:0]

stat_lt_k_p1_from_rx1[1:0]

stat_lt_k_p1_from_rx2[1:0]

stat_lt_k_p1_from_rx3[1:0]

O

rx_serdes_clk

This 2-bit field indicates the update control bits for the k+1 coefficient, as received from the link partner in the control block.

stat_lt_k0_from_rx0[1:0]

stat_lt_k0_from_rx1[1:0]

stat_lt_k0_from_rx2[1:0]

stat_lt_k0_from_rx3[1:0]

O

rx_serdes_clk

This 2-bit field indicates the update control bits for the k0 coefficient, as received from the link partner in the control block.

stat_lt_k_m1_from_rx0[1:0]

stat_lt_k_m1_from_rx1[1:0]

stat_lt_k_m1_from_rx2[1:0]

stat_lt_k_m1_from_rx3[1:0]

O

rx_serdes_clk

This 2-bit field indicates the update control bits for the k-1 coefficient, as received from the link partner in the control block.

stat_lt_stat_p1_from_rx0[1:0]

stat_lt_stat_p1_from_rx1[1:0]

stat_lt_stat_p1_from_rx2[1:0]

stat_lt_stat_p1_from_rx3[1:0]

O

rx_serdes_clk

This 2-bit field indicates the update status bits for the k+1 coefficient, as received from the link partner in the status block.

stat_lt_stat0_from_rx0[1:0]

stat_lt_stat0_from_rx1[1:0]

stat_lt_stat0_from_rx2[1:0]

stat_lt_stat0_from_rx3[1:0]

O

rx_serdes_clk

This 2-bit fields indicates the update status bits for the k0 coefficient, as received from the link partner in the status block.

stat_lt_stat_m1_from_rx0[1:0]

stat_lt_stat_m1_from_rx1[1:0]

stat_lt_stat_m1_from_rx2[1:0]

stat_lt_stat_m1_from_rx3[1:0]

O

rx_serdes_clk

This 2-bit field indicates the update status bits for the k-1 coefficient, as received from the link partner in the status block.

lt_tx_sof[3:0]

O

tx_serdes_clk

This is a link training signal that is asserted for one tx_serdes_clk period at the start of each training frame. It is provided for applications that need to count training frames or synchronize events to the output of the training frames.