OTN Interface Bus Transactions - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203)

Document ID
PG203
Release Date
2022-11-02
Version
3.1 English

This Figure illustrates the bus timing for the OTN interface where OTN_LANES is equal to 5.

Figure B-2: RX OTN Interface Bus Timing

X-Ref Target - Figure B-2

X19886-otn-interface-bus-timing.jpg

The five lanes of data are qualified by the rx_otn_ena enable bus and are only ready when the enable is 1.

When the PCS Lane 0 data is present on the rx_otn_data0 bus, rx_otn_lane0 is asserted.

In this example the alignment markers will be present on the OTN interface for four cycles of data as indicated by the rx_otn_vlmarker signal. When the rx_otn_vlmarker is asserted, the BIP8 value calculated from the received data is presented on the rx_otn_bip8_0 to rx_otn_bip8_4 buses.