The TX interface uses a common clock for all SerDes lanes. However in the RX direction, similar to the distribution of the data streams from the SerDes interface to the PCS lane, the RX PCS lane clocks also change with the operating mode. A hardened clock multiplexer block is used to change the clocking. This Figure illustrates this clock multiplexing by looking at the clock multiplexing required for PCS lanes 0 and 1.
